公开(公告)号：US20090024887A1

公开(公告)日：2009-01-22

申请号：US12032877

申请日：2008-02-18

申请人： Daijiro Kimbara ,  Hiroo Nakano ,  Tetsuro Iwamura ,  Atsushi Kobayashi ,  Masahiko Motoyama ,  Hideki Teraoka ,  Atsushi Shimbo ,  Hideo Shimizu

发明人： Daijiro Kimbara ,  Hiroo Nakano ,  Tetsuro Iwamura ,  Atsushi Kobayashi ,  Masahiko Motoyama ,  Hideki Teraoka ,  Atsushi Shimbo ,  Hideo Shimizu

IPC分类号： G11C29/00

CPC分类号： G06F21/77 ,  G06F11/1016 ,  G06F2221/2121 ,  G06K19/07363 ,  G11C7/1006 ,  G11C2029/0411

摘要： A semiconductor storage device includes an arithmetic operation unit configured to perform an arithmetic operation of generating a different error detecting code depending on the information of a memory address, using the data and the information of the memory address in a memory cell into which the data is written, and a storage unit configured to store the data and the error detecting code in the memory cell.

摘要翻译： 一种半导体存储装置，包括算术运算单元，其被配置为使用数据和存储器单元中的存储器地址的信息，根据存储器地址的信息执行生成不同的检错码的算术运算， 以及存储单元，被配置为将数据和错误检测码存储在存储单元中。

公开(公告)号：US20080215955A1

公开(公告)日：2008-09-04

申请号：US12032872

申请日：2008-02-18

申请人： Daijiro Kimbara ,  Hiroo Nakano ,  Tetsuro Iwamura ,  Atsushi Kobayashi ,  Masahiko Motoyama ,  Hideki Teraoka ,  Atsushi Shimbo ,  Hideo Shimizu

发明人： Daijiro Kimbara ,  Hiroo Nakano ,  Tetsuro Iwamura ,  Atsushi Kobayashi ,  Masahiko Motoyama ,  Hideki Teraoka ,  Atsushi Shimbo ,  Hideo Shimizu

IPC分类号： G11C29/00 ,  G06F11/00

CPC分类号： G06F11/1008

摘要： A semiconductor storage device includes: a memory configured to store data at a first address and store an error detecting code corresponding to the data at a second address which is set up in a predetermined relation with the first address and different from the first address; and an address storage portion configured to store information on address relation between the first address and the second address.

摘要翻译： 半导体存储装置包括：存储器，其被配置为在第一地址处存储数据，并且在与第一地址以预定关系建立并且与第一地址不同的第二地址处存储对应于数据的错误检测码; 以及地址存储部，被配置为存储关于所述第一地址和所述第二地址之间的地址关系的信息。

公开(公告)号：US20120072646A1

公开(公告)日：2012-03-22

申请号：US13053397

申请日：2011-03-22

申请人： Hiroo Nakano

发明人： Hiroo Nakano

IPC分类号： G06F12/00

CPC分类号： G11C16/06 ,  G11C16/14 ,  G11C16/22

摘要： According to one embodiment, a semiconductor integrated circuit device includes a non-volatile memory, a storing module, and a processing module. The non-volatile memory is having a first area and a second area. The storing module is configured to store a second program for downloading a first program from an outside to the first area. The processing module is configured to execute the first and the second programs. The non-volatile memory is having a first area and a second area. The storing module is configured to store a second program for downloading a first program from an outside to the first area. The processing module is configured to execute the first and the second programs. The first area is capable of being written and erased by the first program, and the second area is not capable of being erased by the first program.

摘要翻译： 根据一个实施例，半导体集成电路器件包括非易失性存储器，存储模块和处理模块。 非易失性存储器具有第一区域和第二区域。 存储模块被配置为存储用于将第一程序从外部下载到第一区域的第二程序。 处理模块被配置为执行第一和第二程序。 非易失性存储器具有第一区域和第二区域。 存储模块被配置为存储用于将第一程序从外部下载到第一区域的第二程序。 处理模块被配置为执行第一和第二程序。 第一个区域能够由第一个程序写入和擦除，第二个区域不能被第一个程序擦除。

公开(公告)号：US06575373B1

公开(公告)日：2003-06-10

申请号：US09662864

申请日：2000-09-15

申请人： Hiroo Nakano

发明人： Hiroo Nakano

IPC分类号： G06K1906

CPC分类号： G06F21/77 ,  G06F9/3869 ,  G06F21/75 ,  G06F21/755 ,  G06F2207/7219 ,  G06K19/073 ,  G06K19/07363

摘要： A security card 20 including a CPU 1 for executing instruction sequences such as a password verifying routine, a memory 2 configured to store secret data such as the password and so forth, a random signal generation circuit 4 configured to generate a wait signal which is output in order to halt the operation of the CPU 1. When the wait signal is input, the CPU 1 halts its operation for a short time such as one to several clocks. In accordance with the security card 20, the operation of the CPU 1 can be deferred for a short time in an arbitrary timing in order to make it difficult to analyze the operation of the CPU 1.

摘要翻译： 包括用于执行诸如密码验证程序等指令序列的CPU1的安全卡20，配置为存储诸如密码等的秘密数据的存储器2，被配置为生成输出的等待信号的随机信号生成电路4 以便停止CPU 1的操作。当等待信号被输入时，CPU 1将其操作暂停一小到几个时钟的短时间。 根据安全卡20，CPU 1的操作可以在任意定时短时间推迟，以便难以分析CPU 1的操作。

公开(公告)号：US06375082B1

公开(公告)日：2002-04-23

申请号：US09263955

申请日：1999-03-08

申请人： Tsutomu Kobayashi ,  Masatsugu Mukuge ,  Hiroo Nakano ,  Aki Fukuda

发明人： Tsutomu Kobayashi ,  Masatsugu Mukuge ,  Hiroo Nakano ,  Aki Fukuda

IPC分类号： G06K1906

CPC分类号： G06K19/07769 ,  G06K7/0008 ,  G06K19/07 ,  G06K19/0723 ,  G06K19/077

摘要： A portable electronic device has contacting and noncontacting interfaces and an inhibiting section. The contacting interface including a plurality of contact terminals for exchanging driving power and data. The noncontacting interface for generating driving power and demodulating received data from a signal received via an antenna. The inhibiting section for inhibiting an operation of the other one of the contacting and noncontacting interfaces while the portable electronic device is driven via one of the contacting and noncontacting interfaces.

摘要翻译： 便携式电子设备具有接触和非接触界面和抑制部分。 接触界面包括用于交换驱动力和数据的多个接触端子。 用于产生驱动功率并且经由天线接收的信号解调接收数据的非接触接口。 禁止部分，用于在通过接触和非接触接口中的一个驱动便携式电子设备时，禁止另一个接触和非接触接口的操作。

公开(公告)号：US06363456B1

公开(公告)日：2002-03-26

申请号：US09353662

申请日：1999-07-15

申请人： Hiroo Nakano

发明人： Hiroo Nakano

IPC分类号： G06F1200

CPC分类号： G07F7/1008 ,  G06Q20/341 ,  G06Q20/3576

摘要： An IC card according to the present invention includes a communication section for receiving externally transmitted data, a storage section for storing a file and definition information of the file, and a delete section for, when the data received through the communication section is a command to delete a predetermined file, deleting the predetermined file and definition information of the predetermined file from the storage section.

摘要翻译： 根据本发明的IC卡包括用于接收外部发送的数据的通信部分，用于存储文件的存储部分和文件的定义信息;以及删除部分，当通过通信部分接收到的数据是命令 删除预定文件，从存储部分删除预定文件和预定文件的定义信息。

公开(公告)号：US08806107B2

公开(公告)日：2014-08-12

申请号：US13053397

申请日：2011-03-22

申请人： Hiroo Nakano

发明人： Hiroo Nakano

IPC分类号： G06F12/00

CPC分类号： G11C16/06 ,  G11C16/14 ,  G11C16/22

摘要： According to one embodiment, a semiconductor integrated circuit device includes a non-volatile memory, a storing module, and a processing module. The non-volatile memory is having a first area and a second area. The storing module is configured to store a second program for downloading a first program from an outside to the first area. The processing module is configured to execute the first and the second programs. The non-volatile memory is having a first area and a second area. The storing module is configured to store a second program for downloading a first program from an outside to the first area. The processing module is configured to execute the first and the second programs. The first area is capable of being written and erased by the first program, and the second area is not capable of being erased by the first program.

摘要翻译： 根据一个实施例，半导体集成电路器件包括非易失性存储器，存储模块和处理模块。 非易失性存储器具有第一区域和第二区域。 存储模块被配置为存储用于将第一程序从外部下载到第一区域的第二程序。 处理模块被配置为执行第一和第二程序。 非易失性存储器具有第一区域和第二区域。 存储模块被配置为存储用于将第一程序从外部下载到第一区域的第二程序。 处理模块被配置为执行第一和第二程序。 第一个区域能够由第一个程序写入和擦除，第二个区域不能被第一个程序擦除。

公开(公告)号：US06735105B2

公开(公告)日：2004-05-11

申请号：US10277050

申请日：2002-10-22

申请人： Hiroo Nakano

发明人： Hiroo Nakano

IPC分类号： G11C502

CPC分类号： G06K19/0701 ,  G06K19/0715 ,  G06K19/0723 ,  G06K19/073

摘要： A semiconductor circuit having a power supply voltage detection circuit to detect a potential level of an external power supply voltage and to output a detection signal depending on a comparison result with the potential level. A system control circuit detects the detection signal, outputs a status signal and an interrupt signal, and outputs a clock selection signal in response to an operation control signal. A CPU outputs the operation control signal to the system control circuit in response to the status signal and the interrupt signal. A clock generation circuit generates a plurality of clock signals and a clock selection circuit selects one clock signal among the plurality of clock signals in response to the clock selection signal. The clock selection circuit then outputs the one clock signal as a system clock signal.

摘要翻译： 一种具有电源电压检测电路的半导体电路，用于检测外部电源电压的电位电平，并根据与电位电平的比较结果输出检测信号。 系统控制电路检测检测信号，输出状态信号和中断信号，并响应于操作控制信号输出时钟选择信号。 CPU根据状态信号和中断信号将操作控制信号输出到系统控制电路。 时钟发生电路产生多个时钟信号，并且时钟选择电路响应于时钟选择信号选择多个时钟信号中的一个时钟信号。 然后时钟选择电路输出一个时钟信号作为系统时钟信号。

公开(公告)号：US5185082A

公开(公告)日：1993-02-09

申请号：US894544

申请日：1992-06-05

申请人： Hiroo Nakano ,  Seiichi Manabe

发明人： Hiroo Nakano ,  Seiichi Manabe

IPC分类号： A61L2/02 ,  B01D65/10

CPC分类号： B01D65/102 ,  A61L2/022 ,  B01D65/104

摘要： Disclosed is a method for the evaluation of the virus-removing capability of a porous polymeric membrane module for removing viruses by filtration, which comprises testing I in which a transmembrane pressure lowering from predetermined value Ph a predetermined period of time after the termination of the supply of a gas is measured with respect to the porous polymeric membrane module, wherein the value Ph satisfies the formula: d

公开(公告)号：US4787977A

公开(公告)日：1988-11-29

申请号：US797973

申请日：1985-11-14

申请人： Hiroo Nakano ,  Kazushige Seita ,  Kazuo Imamura ,  Tetsuo Watanabe

发明人： Hiroo Nakano ,  Kazushige Seita ,  Kazuo Imamura ,  Tetsuo Watanabe

IPC分类号： A61L33/06 ,  B01D67/00 ,  B01D71/10 ,  A61M1/34 ,  B01D13/01

CPC分类号： B01D67/0088 ,  A61L33/064 ,  B01D71/10

摘要： A blood-purifying regenerated cellulose membrane, in which the occurrence of the leukopenia phenomenon and the activation of the complement system are moderated, is prepared by applying a solution of a polymeric substance comprising as one component units derived from one or more basic vinyl monomers having an amino group in the side chain in an organic solvent to a regenerated cellulose membrane, removing the excessive solution, and then fixing the polymeric substance to the regenerated cellulose membrane.

摘要翻译： 通过施加包含衍生自一种或多种碱性乙烯基单体的单体组分的聚合物质的溶液来制备血白素再生纤维素膜，其中发生白细胞减少现象和补体系统的活化， 将有机溶剂中的侧链中的氨基与再生纤维素膜反应，除去过量的溶液，然后将聚合物固定在再生纤维素膜上。