摘要:
A security system including several camera devices and a communication device in sites at which monitoring is required by a user. The several camera devices may constantly monitor the sites. The camera devices have motion detecting functions and provide unusual status reporting signals and necessary image information to the communications device when the movements of an intruder have been detected. The communication device communicates with and is connected to a server that serves as an information center via the internet line when unusual status signals have been received. The information from the camera devices is also sent to server. The server automatically notifies the user by a predetermined user-selected method. The notified user can access the server and confirm the information.
摘要:
An automatic vessel position holding control method for holding a vessel position and a vessel heading of a vessel on the ocean in order to reduce a positional deviation and a heading deviation sharply as compared with the conventional automatic vessel position holding control by performing feedforward control for estimating and then compensating at least one of a wave drifting force and a wave drifting moment that act on the vessel, wherein a vessel position holding control is performed that includes such controls as estimating waves entering the vessel from motion thereof, calculating at least one of the wave drifting force and the wave drifting moment from the estimated waves and performing feedforward control for at least one of the calculated wave drifting force and the calculated wave drifting moment.
摘要:
A timing generator having no dead time and capable of altering a timing at any time. A rough timing pulse generating means suitably specifies one of a plurality of input clock pulses to generate a rough timing pulse for a desired timing. A timing vernier delays the rough timing pulse for a suitable delay time to generate a minute timing pulse. In a compensating circuit, the minute timing pulse is input to a delay circuit having one input terminal and plural output terminals, and one of the outputs at the output terminals for delay is selected by a multiplexer. When the multiplexer selects an output whose delay time is not zero, a next pulse can be input from the timing vernier to the dead time compensating circuit so that no dead time occurs.
摘要:
An automatic vessel position holding control method for holding a vessel position and a vessel heading of a vessel on the ocean in order to reduce a positional deviation and a heading deviation sharply as compared with the conventional automatic vessel position holding control by performing feedforward control for estimating and then compensating for at least one of a wave drifting force and a wave drifting moment that act on the vessel, wherein a vessel position holding control is performed that includes such controls as estimating waves entering the vessel from motion thereof, calculating at least one of the wave drifting force and the wave drifting moment from the estimated waves and performing feedforward control for at least one of the calculated wave drifting force and the calculated wave drifting moment.
摘要:
An automatic vessel position holding control method for holding a vessel position and a vessel heading of a vessel on the ocean in order to reduce a positional deviation and a heading deviation sharply as compared with the conventional automatic vessel position holding control by performing feedforward control for estimating and then compensating for at least one of a wave drifting force and a wave drifting moment that act on the vessel, wherein a vessel position holding control is performed that includes such controls as estimating waves entering the vessel from motion thereof, calculating at least one of the wave drifting force and the wave drifting moment from the estimated waves and performing feedforward control for at least one of the calculated wave drifting force and the calculated wave drifting moment.
摘要:
A memory access system and method is provided to modify a memory interleaving scheme so that data can be read from a memory system in any sequence without inserting a waiting cycle. Even addressees are assigned to a first memory bank and odd addresses to a second memory bank. If a sequential address sequence is being provided, the first and second memory banks are read alternately. A third memory bank is provided which has the contents of both first and second memory banks. When an address sequence is detected that successively accesses either the first memory bank or the second memory bank, the access is switched to the third memory bank.