公开(公告)号：US5136180A

公开(公告)日：1992-08-04

申请号：US655018

申请日：1991-02-12

申请人： Kenneth P. Caviasca ,  Tein-Yow Yu ,  Ned D. Garinger ,  Pratiksh Parikh ,  W. Henry Potts ,  James B. Nolan

发明人： Kenneth P. Caviasca ,  Tein-Yow Yu ,  Ned D. Garinger ,  Pratiksh Parikh ,  W. Henry Potts ,  James B. Nolan

IPC分类号： G06F1/08

CPC分类号： G06F1/08

摘要： A circuit generates a system clock signal. On a first input of the circuit a first oscillating signal is placed. On a second input, a second oscillating signal may be placed. Clock sense logic is connected to the second input. The clock sense logic detects whether the second oscillation signal is present on the second input. When the second oscillating signal is not present on the second input, the first oscillating signal is selected to be used to generate the system clock. When the second oscillating signal is present on the second input, the second oscillating signal is selected to be used to generate the system clock. The selected oscillating signal is divided to produce the system clock signal. A first frequency divider divides the selected oscillating signal by a first amount. In parallel, a second frequency divider divides the selected oscillating signal by a second amount. A selector, for example, a multiplexor, selects output from either the first frequency divider or the second frequency divider as the system clock signal. When the first oscillating signal is being used to generate the system clock, the second input may be used to control the selection of frequency dividers.

摘要翻译： 电路产生系统时钟信号。 在电路的第一输入端放置第一振荡信号。 在第二输入端，可以放置第二振荡信号。 时钟检测逻辑连接到第二个输入。 时钟感测逻辑检测第二振荡信号是否存在于第二输入端。 当第二输入端不存在第二振荡信号时，选择第一振荡信号来产生系统时钟。 当第二振荡信号存在于第二输入端时，第二振荡信号被选择用于产生系统时钟。 所选择的振荡信号被分频以产生系统时钟信号。 第一分频器将选择的振荡信号除以第一量。 并行地，第二分频器将所选择的振荡信号除以第二量。 选择器，例如，多路复用器，选择来自第一分频器或第二分频器的输出作为系统时钟信号。 当第一个振荡信号用于产生系统时钟时，第二个输入可用于控制分频器的选择。

公开(公告)号：US6145047A

公开(公告)日：2000-11-07

申请号：US245950

申请日：1994-05-19

申请人： Ned D. Garinger ,  Tein-Yow Yu

发明人： Ned D. Garinger ,  Tein-Yow Yu

IPC分类号： G06F13/24 ,  G06F9/46

CPC分类号： G06F13/24

摘要： Level trigger mode interrupts are converted to edge trigger mode interrupts in a computer system. A circuit detects the occurrence of a level trigger mode interrupt request, and asserts an edge trigger mode interrupt request output. The edge trigger mode interrupt request remains asserted until an End of Interrupt input is asserted, indicating that the CPU has completed servicing the prior interrupt. The edge trigger mode interrupt request is then deasserted.

摘要翻译： 电平触发模式中断在计算机系统中转换为边沿触发模式中断。 电路检测到电平触发模式中断请求的发生，并且断言边沿触发模式中断请求输出。 边沿触发模式中断请求保持置位，直到中断输入结束为止，表明CPU已经完成对先前中断的服务。 然后边沿触发模式中断请求被置为无效。

公开(公告)号：US07684404B1

公开(公告)日：2010-03-23

申请号：US10866125

申请日：2004-06-10

申请人： Eduard Lecha ,  Ramji Pankhaniya ,  Tein-Yow Yu

发明人： Eduard Lecha ,  Ramji Pankhaniya ,  Tein-Yow Yu

IPC分类号： H04L12/28 ,  H04L12/56 ,  H01J3/16 ,  H01J3/22

CPC分类号： H04L12/5601

摘要： A method for formatting ATM cells compliant with SPI-4 Phase 2 specification is presented. The method enables selection among various cell formats depending on the devices employed, and enables use of a payload-only test format, a typical format having payload and header data, a format having header error correction (HEC) data and dummy data, and a format having HEC data and user data.

摘要翻译： 提出了一种格式化符合SPI-4 Phase 2规范的ATM信元的方法。 该方法能够根据所采用的装置进行各种单元格式的选择，并且能够使用仅有效载荷的测试格式，具有有效载荷和头部数据的典型格式，具有头部纠错（HEC）数据和伪数据的格式，以及 格式具有HEC数据和用户数据。

公开(公告)号：US06584145B1

公开(公告)日：2003-06-24

申请号：US09324411

申请日：1999-06-02

申请人： John Camagna ,  Tein-Yow Yu ,  James Ward Girardeau, Jr.

发明人： John Camagna ,  Tein-Yow Yu ,  James Ward Girardeau, Jr.

IPC分类号： H03M100

CPC分类号： H03H17/0628 ,  H03H17/0621 ,  H03H2218/10 ,  H04L7/0029

摘要： A converter or a resampler used in a digital communication system converts a first digital signal representing an analog signal into a second digital signal representing the same analog signal. The converter includes a converter filter and a timing circuit. The timing circuit provides a first clock generated from a second clock, and a phase control signal for controlling the conversion of the converter filter. The timing circuit is preferably a numerical controlled oscillator (NCO) and includes an accumulator for generating the first clock from the second clock and a phase offset, and a phase calculator which receives the phase offset to generate a phase control signal. The phase control signal includes a plurality of phase weighting signals, a plurality of control signals, and an interpolation signal. The first digital signal is selectively convoluted with the phase weighting signals, which is controlled by the control signals. The convoluted signals are interpolated by the interpolation signal to generate the second digital signal.

摘要翻译： 在数字通信系统中使用的A转换器或重采样器将表示模拟信号的第一数字信号转换为表示相同模拟信号的第二数字信号。 转换器包括转换器滤波器和定时电路。 定时电路提供从第二时钟产生的第一时钟，以及用于控制转换器滤波器的转换的相位控制信号。 定时电路优选地是数控振荡器（NCO），并且包括用于从第二时钟产生第一时钟和相位偏移的累加器，以及接收相位偏移以产生相位控制信号的相位计算器。 相位控制信号包括多个相位加权信号，多个控制信号和内插信号。 第一数字信号与由控制信号控制的相位加权信号选择性地卷积。 通过内插信号对卷积信号进行内插以产生第二数字信号。

公开(公告)号：US5651040A

公开(公告)日：1997-07-22

申请号：US646043

申请日：1996-05-07

申请人： Tein-Yow Yu

发明人： Tein-Yow Yu

IPC分类号： G01R31/3185 ,  H03K21/40

CPC分类号： G01R31/318527 ,  G06F2201/88

摘要： A method and system for testing a digital counter of mn bits comprises dividing the counter into m segments, each of n bits. For test purposes, the counter then is further divided into first and second m segment groups. Multiplex gates are used between the segments and are controlled by sensing the condition of the most significant bits of the most significant one of the m segments for applying clock pulses to verify specific connections between various bits of the counter for the first four cycles of clock pulses applied during the test mode. After these four cycles, gating circuits coupled with the most significant bits of the most significant one of the m segments are used to automatically switch the remainder of the test connections to the second group to verify all of the remaining connections in the counter, with full testing of the counter being accomplished in 2.sup.n +2 cycles of clock pulses.

摘要翻译： 用于测试mn位的数字计数器的方法和系统包括将计数器分成m个段，每个n位。 为了测试目的，计数器然后进一步分为第一和第二m个段组。 多个门用于段之间，并且通过感测m个段中最高有效位之一的最高有效位的条件来控制，以施加时钟脉冲，以验证计数器的各个比特之间在时钟脉冲的前四个周期中的特定连接 在测试模式下应用。 在这四个周期之后，选通电路与m段中最重要的一个之间的最高有效位相耦合，用于自动将剩余的测试连接切换到第二组，以验证计数器中的所有剩余连接，并将其全部 在2n + 2个时钟脉冲周期内对计数器进行测试。