公开(公告)号：US20050033925A1

公开(公告)日：2005-02-10

申请号：US10655661

申请日：2003-09-05

申请人： Kenneth Wilson ,  Fong Pong ,  Lance Russell ,  Tung Nguyen ,  Lu Xu

发明人： Kenneth Wilson ,  Fong Pong ,  Lance Russell ,  Tung Nguyen ,  Lu Xu

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0808 ,  G06F12/0804 ,  G06F12/0817 ,  G06F2212/2542

摘要： A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the recall unit, a recall (“flush”) command is issued which forces the owner cache to write-back the dirty cache line to be flushed. The memory controller will inform the recall unit as each recall operation is completed. The recall unit operation will be interrupted when all flush requests are completed.

摘要翻译： 高速缓存一致分布式共享存储器多处理器计算机系统具有包括调用单元的存储器控​​制器。 调用单元允许将脏的高速缓存行的选择性强制回写到家庭存储器。 在调用单元中发布请求后，会发出召回（“flush”）命令，强制所有者高速缓存写回要清除的脏高速缓存行。 每次召回操作完成后，存储器控制器将通知召回单元。 所有刷新请求完成后，调用单元操作将中断。

公开(公告)号：US07120752B2

公开(公告)日：2006-10-10

申请号：US10655661

申请日：2003-09-05

申请人： Kenneth Mark Wilson ,  Fong Pong ,  Lance Russell ,  Tung Nguyen ,  Lu Xu

发明人： Kenneth Mark Wilson ,  Fong Pong ,  Lance Russell ,  Tung Nguyen ,  Lu Xu

IPC分类号： G06F12/00

CPC分类号： G06F12/0808 ,  G06F12/0804 ,  G06F12/0817 ,  G06F2212/2542

摘要： A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the recall unit, a recall (“flush”) command is issued which forces the owner cache to write-back the dirty cache line to be flushed. The memory controller will inform the recall unit as each recall operation is completed. The recall unit operation will be interrupted when all flush requests are completed.

摘要翻译： 高速缓存一致分布式共享存储器多处理器计算机系统具有包括调用单元的存储器控​​制器。 调用单元允许将脏的高速缓存行的选择性强制回写到家庭存储器。 在调用单元中发布请求后，会发出召回（“flush”）命令，强制所有者高速缓存写回要清除的脏高速缓存行。 每次召回操作完成后，存储器控制器将通知召回单元。 所有刷新请求完成后，调用单元操作将中断。

公开(公告)号：US06745294B1

公开(公告)日：2004-06-01

申请号：US09877539

申请日：2001-06-08

申请人： Kenneth Mark Wilson ,  Fong Pong ,  Lance Russell ,  Tung Nguyen ,  Lu Xu

发明人： Kenneth Mark Wilson ,  Fong Pong ,  Lance Russell ,  Tung Nguyen ,  Lu Xu

IPC分类号： G06F1200

CPC分类号： G06F12/0808 ,  G06F12/0804

摘要： A method is provided for cache flushing in a computer system having a processor, a cache, a synchronization primitive detector, and a cache flush engine. The method includes providing a synchronization primitive from the processor into the computer system; detecting the synchronization primitive in the synchronization primitive detector; providing a trigger signal from the synchronization primitive detector in response to detection of the synchronization primitive; providing cache information from the recall unit into the computer system in response to the trigger signal; and flushing the cache in response to the cache information in the computer system.

摘要翻译： 提供了一种用于具有处理器，高速缓存，同步原语检测器和高速缓存冲洗引擎的计算机系统中的高速缓存冲洗的方法。 该方法包括从处理器向计算机系统提供同步原语; 检测同步原语检测器中的同步原语; 响应于同步原语的检测，提供来自同步原语检测器的触发信号; 响应于所述触发信号，从所述调用单元向计算机系统提供高速缓存信息; 并响应于计算机系统中的缓存信息来刷新高速缓存。

公开(公告)号：US06675262B1

公开(公告)日：2004-01-06

申请号：US09877368

申请日：2001-06-08

申请人： Kenneth Mark Wilson ,  Fong Pong ,  Lance Russell ,  Tung Nguyen ,  Lu Xu

发明人： Kenneth Mark Wilson ,  Fong Pong ,  Lance Russell ,  Tung Nguyen ,  Lu Xu

IPC分类号： G06F1200

CPC分类号： G06F12/0808 ,  G06F12/0804 ,  G06F12/0817 ,  G06F2212/2542

摘要： A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the recall unit, a recall (“flush”) command is issued which forces the owner cache to write-back the dirty cache line to be flushed. The memory controller will inform the recall unit as each recall operation is completed. The recall unit operation will be interrupted when all flush requests are completed.

摘要翻译： 高速缓存一致分布式共享存储器多处理器计算机系统具有包括调用单元的存储器控​​制器。 调用单元允许将脏的高速缓存行的选择性强制回写到家庭存储器。 在调用单元中发布请求后，会发出召回（“flush”）命令，强制所有者高速缓存写回要清除的脏高速缓存行。 每次召回操作完成后，存储器控制器将通知召回单元。 所有刷新请求完成后，调用单元操作将中断。

公开(公告)号：US06360231B1

公开(公告)日：2002-03-19

申请号：US09258608

申请日：1999-02-26

申请人： Fong Pong ,  Lance Russell ,  Tung Nguyen

发明人： Fong Pong ,  Lance Russell ,  Tung Nguyen

IPC分类号： G06F1730

CPC分类号： G06F12/0815 ,  Y10S707/99952

摘要： A cache coherent distributed shared memory multi-processor computer system is provided which supports transactional memory semantics. A cache flushing engine and temporary buffer allow selective forced write-backs of dirty cache lines to the home memory. A flush can be performed from the updated cache to the temporary buffer and then to the home memory after confirmation of receipt or from the updated cache to the home memory directly with the temporary buffer holding the old data until confirmation that the home memory contains the update.

摘要翻译： 提供了一种支持事务性存储器语义的高速缓存一致分布式共享存储器多处理器计算机系统。 高速缓存刷新引擎和临时缓冲区允许有选择地将脏缓存行强制回写到家庭存储器。 可以在保存了旧数据的临时缓冲器之后，从更新的缓存到临时缓冲区执行刷新，然后在确认接收之后到家庭存储器或从更新的高速缓存直接到家庭存储器，直到确认家庭存储器包含更新 。

公开(公告)号：US06880045B2

公开(公告)日：2005-04-12

申请号：US09976495

申请日：2001-10-12

申请人： Fong Pong ,  Lance Russell ,  Tung Nguyen

发明人： Fong Pong ,  Lance Russell ,  Tung Nguyen

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0815 ,  Y10S707/99952

摘要： A cache coherent distributed shared memory multi-processor computer system is provided which supports transactional memory semantics. A cache flushing engine and temporary buffer allow selective forced write-backs of dirty cache lines to the home memory. A flush can be performed from the updated cache to the temporary buffer and then to the home memory after confirmation of receipt or from the updated cache to the home memory directly with the temporary buffer holding the old data until confirmation that the home memory contains the update.

摘要翻译： 提供了一种支持事务性存储器语义的高速缓存一致分布式共享存储器多处理器计算机系统。 高速缓存刷新引擎和临时缓冲区允许有选择地将脏缓存行强制回写到家庭存储器。 可以在保存了旧数据的临时缓冲器之后，从更新的缓存到临时缓冲区执行刷新，然后在确认接收之后到家庭存储器或从更新的高速缓存直接到家庭存储器，直到确认家庭存储器包含更新 。

公开(公告)号：US06874065B1

公开(公告)日：2005-03-29

申请号：US09258549

申请日：1999-02-26

申请人： Fong Pong ,  Lance Russell ,  Tung Nguyen

发明人： Fong Pong ,  Lance Russell ,  Tung Nguyen

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0813 ,  G06F12/0804 ,  G06F12/0817 ,  G06F2212/2542

摘要： A cache coherent distributed shared memory multi-processor computer system is provided with a cache-flushing engine which allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the cache-flushing engine, a “flush” command is issued which forces the owner cache to write-back the dirty cache line to be flushed. Subsequently, a “flush request” is issued to the home memory of the memory block. The home node will acknowledge when the home memory is successfully updated. The cache-flushing engine operation will be interrupted when all flush requests are complete.

摘要翻译： 高速缓存一致的分布式共享存储器多处理器计算机系统具有缓存刷新引擎，其允许将脏的高速缓存行选择性强制回写到家庭存储器。 在缓存刷新引擎中发布请求之后，会发出一个“刷新”命令，强制所有者缓存将要清除的脏缓存行写回。 随后，向存储块的归属存储器发出“刷新请求”。 当家庭存储器成功更新时，家庭节点将确认。 当所有刷新请求完成时，缓存刷新引擎操作将中断。

公开(公告)号：US06728843B1

公开(公告)日：2004-04-27

申请号：US09451499

申请日：1999-11-30

申请人： Fong Pong ,  Tung Nguyen

发明人： Fong Pong ,  Tung Nguyen

IPC分类号： G06F1200

CPC分类号： G06F12/0828

摘要： A system and method for processing multiple main memory accesses in parallel includes transmitting from the processor to the system control unit a first and a second transaction. These transactions are decoded to determine their corresponding commands and addresses. The system control unit includes a qualifier and a scheduler that assigns each transaction to a particular finite state machine (FSM). Each FSM executes a single transaction until completed. Each FSM machine maintains a record or keeps track of the state of progress of a transaction that is being executed by the system control unit. The FSMs keep track of the data by storing the data, such as the current state of the transaction, the status of the data, and an identifier describing which processor issued the transaction, for each transaction in a data buffer. The data value corresponding to a particular transaction may be retrieved from the main memory using a FSM. Since a different FSM is used to retrieve data values, the execution of these transactions can be performed in parallel. Parallel processing of memory accesses using FSMs enhances the speed and efficiency of computer systems.

摘要翻译： 用于并行处理多个主存储器访问的系统和方法包括从处理器向系统控制单元发送第一和第二事务。 这些事务被解码以确定它们相应的命令和地址。 系统控制单元包括限定器和调度器，其将每个事务分配给特定的有限状态机（FSM）。 每个FSM执行一个事务直到完成。 每个FSM机器维护记录或跟踪系统控制单元正在执行的事务的进展状态。 FSM通过存储数据来跟踪数据，例如数据的当前状态，数据的状态以及描述哪个处理器发出交易的标识符，用于数据缓冲器中的每个事务。 可以使用FSM从主存储器检索对应于特定事务的数据值。 由于使用不同的FSM来检索数据值，因此可以并行执行这些事务。 使用FSM并行处理存储器访问可提高计算机系统的速度和效率。

公开(公告)号：US06490662B1

公开(公告)日：2002-12-03

申请号：US09561755

申请日：2000-04-29

申请人： Fong Pong ,  Tung Nguyen

发明人： Fong Pong ,  Tung Nguyen

IPC分类号： G06F1200

CPC分类号： G06F11/183 ,  G06F11/1666 ,  G06F11/18 ,  G06F12/0815

摘要： A computer system and method for enhancing the reliability of a computer system by combining a cache sync-flush engine with a replicated memory module includes placing a “lock” command on the common bus. The lock protects or controls accesses to a number of memory locations in the memory modules designated by the programmer. At any point in time, one processor can obtain the lock, and hence has access to the number of memory locations protected by the lock. Other processors may attempt to acquire or make a request for the same lock, however, the other processor will fail until the processor that has the lock has released (i.e., “unlocked”) the lock. The other processors will keep trying to get the lock. The processor that obtains the lock instructs the system control unit to begin logging or monitoring all subsequent memory addresses that appear on the common bus. After the processor gets the lock, it can start reading from and writing to the number of memory locations that are implemented as a number of replicated memory modules. A data value is then determined based on the data held by a majority of the replicated memory modules. The data value is transmitted to the cache of the processor. After the data is processed, an “unlock” command is transmitted from the processor to a system control unit that issues a write back request on the common bus that flushes the data value from the cache to the number of replicated memory modules.

摘要翻译： 通过将高速缓存同步冲洗引擎与复制的存储器模块组合来提高计算机系统的可靠性的计算机系统和方法包括在公共总线上放置“锁定”命令。 该锁保护或控制对由编程器指定的存储器模块中的多个存储器位置的访问。 在任何时间点，一个处理器可以获得锁定，因此可以访问被锁定保护的存储器位置的数量。 其他处理器可能尝试获取或请求相同的锁，但是，其他处理器将失败，直到具有锁的处理器已经释放（即，“解锁”）该锁。 其他处理器将继续尝试锁定。 获取锁的处理器指示系统控制单元开始记录或监视公共总线上出现的所有后续存储器地址。 处理器获得锁定后，它可以开始读取和写入实现为多个复制的内存模块的内存位置数。 然后基于大多数复制的存储器模块保存的数据来确定数据值。 数据值被发送到处理器的高速缓存。 在处理数据之后，从处理器向系统控制单元发送“解锁”命令，该系统控制单元在将数据值从高速缓存刷新到复制的存储器模块的数量的公共总线上发出回写请求。

公开(公告)号：US06516343B1

公开(公告)日：2003-02-04

申请号：US09557380

申请日：2000-04-24

申请人： Fong Pong ,  Tung Nguyen

发明人： Fong Pong ,  Tung Nguyen

IPC分类号： G06F1300

CPC分类号： G06F13/1657 ,  G06F12/0808

摘要： A computer system and method for enhancing memory-to-memory copy operations includes transmitting from the processor to the source system control unit a plurality of memory-to-memory copy transactions where each transaction includes a source address and a destination address. A lookup operation is performed on the destination address to determine the destination system control unit that controls access to the destination memory which contains the destination address. A number of data blocks located at the source address in the source memory are retrieved and transmitted to the destination address. The number of data blocks are stored at the destination address in the destination memory.

摘要翻译： 用于增强存储器到存储器复制操作的计算机系统和方法包括从处理器向源系统控制单元发送多个存储器到存储器复制事务，其中每个事务包括源地址和目的地地址。 对目的地址执行查找操作，以确定控制对包含目的地地址的目的地存储器的访问的目的地系统控制单元。 位于源存储器中的源地址处的多个数据块被检索并发送到目的地址。 数据块的数量存储在目的地存储器中的目的地址中。