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1.发明授权Multi-processor computer system with cache-flushing system using memory recall 有权具有缓存刷新系统的多处理器计算机系统使用存储器调用公开(公告)号：US06675262B1
公开(公告)日：2004-01-06
申请号：US09877368
申请日：2001-06-08
申请人： Kenneth Mark Wilson , Fong Pong , Lance Russell , Tung Nguyen , Lu Xu
发明人： Kenneth Mark Wilson , Fong Pong , Lance Russell , Tung Nguyen , Lu Xu
IPC分类号： G06F1200
CPC分类号： G06F12/0808 , G06F12/0804 , G06F12/0817 , G06F2212/2542
摘要： A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the recall unit, a recall (“flush”) command is issued which forces the owner cache to write-back the dirty cache line to be flushed. The memory controller will inform the recall unit as each recall operation is completed. The recall unit operation will be interrupted when all flush requests are completed.
摘要翻译： 高速缓存一致分布式共享存储器多处理器计算机系统具有包括调用单元的存储器控制器。 调用单元允许将脏的高速缓存行的选择性强制回写到家庭存储器。 在调用单元中发布请求后，会发出召回（“flush”）命令，强制所有者高速缓存写回要清除的脏高速缓存行。 每次召回操作完成后，存储器控制器将通知召回单元。 所有刷新请求完成后，调用单元操作将中断。
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2.发明授权公开(公告)号：US06745294B1
公开(公告)日：2004-06-01
申请号：US09877539
申请日：2001-06-08
申请人： Kenneth Mark Wilson , Fong Pong , Lance Russell , Tung Nguyen , Lu Xu
发明人： Kenneth Mark Wilson , Fong Pong , Lance Russell , Tung Nguyen , Lu Xu
IPC分类号： G06F1200
CPC分类号： G06F12/0808 , G06F12/0804
摘要： A method is provided for cache flushing in a computer system having a processor, a cache, a synchronization primitive detector, and a cache flush engine. The method includes providing a synchronization primitive from the processor into the computer system; detecting the synchronization primitive in the synchronization primitive detector; providing a trigger signal from the synchronization primitive detector in response to detection of the synchronization primitive; providing cache information from the recall unit into the computer system in response to the trigger signal; and flushing the cache in response to the cache information in the computer system.
摘要翻译： 提供了一种用于具有处理器，高速缓存，同步原语检测器和高速缓存冲洗引擎的计算机系统中的高速缓存冲洗的方法。 该方法包括从处理器向计算机系统提供同步原语; 检测同步原语检测器中的同步原语; 响应于同步原语的检测，提供来自同步原语检测器的触发信号; 响应于所述触发信号，从所述调用单元向计算机系统提供高速缓存信息; 并响应于计算机系统中的缓存信息来刷新高速缓存。
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3.发明授权Multi-processor computer system with cache-flushing system using memory recall 失效具有缓存刷新系统的多处理器计算机系统使用存储器调用公开(公告)号：US07120752B2
公开(公告)日：2006-10-10
申请号：US10655661
申请日：2003-09-05
申请人： Kenneth Mark Wilson , Fong Pong , Lance Russell , Tung Nguyen , Lu Xu
发明人： Kenneth Mark Wilson , Fong Pong , Lance Russell , Tung Nguyen , Lu Xu
IPC分类号： G06F12/00
CPC分类号： G06F12/0808 , G06F12/0804 , G06F12/0817 , G06F2212/2542
摘要： A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the recall unit, a recall (“flush”) command is issued which forces the owner cache to write-back the dirty cache line to be flushed. The memory controller will inform the recall unit as each recall operation is completed. The recall unit operation will be interrupted when all flush requests are completed.
摘要翻译： 高速缓存一致分布式共享存储器多处理器计算机系统具有包括调用单元的存储器控制器。 调用单元允许将脏的高速缓存行的选择性强制回写到家庭存储器。 在调用单元中发布请求后，会发出召回（“flush”）命令，强制所有者高速缓存写回要清除的脏高速缓存行。 每次召回操作完成后，存储器控制器将通知召回单元。 所有刷新请求完成后，调用单元操作将中断。
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公开(公告)号：US07003646B2
公开(公告)日：2006-02-21
申请号：US10106025
申请日：2002-03-27
申请人： Sumit Roy , Kenneth Mark Wilson
发明人： Sumit Roy , Kenneth Mark Wilson
IPC分类号： G06F12/00
CPC分类号： G06F12/023 , G06F12/08 , G06F2212/401
摘要： In a method for optimizing performance in a memory system, a data structure configured to provide at least one free block of memory is received in the memory system. At least one bucket of memory is released in a swap device of the memory system corresponding to at least one free block of memory provided by the data structure.
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5.发明授权Method and system for creating secure address space using hardware memory router 有权使用硬件内存路由器创建安全地址空间的方法和系统公开(公告)号：US06915402B2
公开(公告)日：2005-07-05
申请号：US09864527
申请日：2001-05-23
CPC分类号： G06F13/1657
摘要： A method and system providing dynamic allocation of memory through hardware is disclosed. An embodiment provides for a multi-processor system providing for a secure partitioned memory. The system comprises a processor(s), a hardware implemented memory router coupled to the processor(s), and memory coupled to the memory router. The memory router stores memory partition information, which describes the memory allocated to the processor(s). Furthermore, the memory router maps a memory access request from a processor to an address in the memory.
摘要翻译： 公开了一种通过硬件提供动态分配存储器的方法和系统。 实施例提供了提供安全分区存储器的多处理器系统。 该系统包括处理器，耦合到处理器的硬件实现的存储器路由器，以及耦合到存储器路由器的存储器。 存储器路由器存储存储器分区信息，其描述分配给处理器的存储器。 此外，存储器路由器将存储器访问请求从处理器映射到存储器中的地址。
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6.发明授权Processor with a general register set that includes address translation registers 有权具有包含地址转换寄存器的通用寄存器集的处理器公开(公告)号：US06766435B1
公开(公告)日：2004-07-20
申请号：US09583795
申请日：2000-05-31
IPC分类号： G06F1206
CPC分类号： G06F12/10 , G06F9/30101 , G06F12/1027 , Y02D10/13
摘要： A processor having one or more address translation registers for holding translation information that enables translations from virtual addresses to physical addresses. The address translation registers may be allocated to a set of logical areas of a process and the logical areas may be allocated to physical pages so as to enhance a likelihood that translation information for the process will be available in the address translation registers. The address translation registers are saved and restored during context switches. The address translation registers may be used with or without translation look-aside buffers.
摘要翻译： 具有一个或多个地址转换寄存器的处理器，用于保持能够从虚拟地址到物理地址的转换的转换信息。 地址转换寄存器可以被分配给一个进程的一组逻辑区域，并且逻辑区域可以被分配给物理页面，以便增强该处理的翻译信息在地址转换寄存器中可用的可能性。 地址转换寄存器在上下文切换期间被保存和恢复。 地址转换寄存器可以与或不与翻译旁路缓冲器一起使用。
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公开(公告)号：US06829691B2
公开(公告)日：2004-12-07
申请号：US10187337
申请日：2002-06-28
IPC分类号： G06F1202
CPC分类号： G06F13/1684 , G06F12/08 , G06F2212/401
摘要： The present invention pertains to a system for performing data compression/decompression. The system may have a memory controller with compression/decompression logic. A first memory array may be coupled to the memory controller via a first bus and a second memory array may be coupled to the memory controller via a second bus. The system may also have logic for directing the transfer of data from the first memory array via the first bus to be processed by the compression/decompression logic and then transferred to the second memory array via the second bus.
摘要翻译： 本发明涉及一种用于执行数据压缩/解压缩的系统。 该系统可以具有带压缩/解压缩逻辑的存储器控制器。 第一存储器阵列可以经由第一总线耦合到存储器控制器，并且第二存储器阵列可以经由第二总线耦合到存储器控制器。 系统还可以具有用于经由第一总线来指导来自第一存储器阵列的数据的逻辑，以由压缩/解压缩逻辑处理，然后经由第二总线传送到第二存储器阵列。
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8.发明授权Method and system allowing a single entity to manage memory comprising compressed and uncompressed data 失效允许单个实体管理包含压缩和未压缩数据的存储器的方法和系统公开(公告)号：US06658549B2
公开(公告)日：2003-12-02
申请号：US09863988
申请日：2001-05-22
IPC分类号： G06F1202
CPC分类号： G06F12/1009 , G06F12/08 , G06F2212/401
摘要： A method for adding compressed page tables to an operating system is disclosed. An embodiment provides for a method in which a single entity, for example, an operating system has control of the compression and decompression of data and where the data is stored. When a data access is desired, the method accesses a table specifying the physical memory location of uncompressed data to determine if specified data is in uncompressed memory. The method of this embodiment accesses a table specifying the physical memory location of data in compressed memory to determine if the data is in the compressed memory. The method also access a page directory table to determine the location of the data in virtual memory in the event of a page fault. Then, this embodiment accesses the data based on the table look-up results.
摘要翻译： 公开了一种将压缩页表添加到操作系统的方法。 一个实施例提供了一种方法，其中单个实体（例如，操作系统）具有数据的压缩和解压缩的控制以及数据的存储位置。 当需要数据访问时，该方法访问指定未压缩数据的物理内存位置的表，以确定指定的数据是否在未压缩的存储器中。 该实施例的方法访问指定压缩存储器中的数据的物理存储器位置的表，以确定数据是否在压缩存储器中。 该方法还访问页面目录表，以在页面错误的情况下确定虚拟内存中数据的位置。 然后，本实施例基于表查找结果访问数据。
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公开(公告)号：US06567907B1
公开(公告)日：2003-05-20
申请号：US09691973
申请日：2000-10-19
IPC分类号： G06F1200
CPC分类号： G06F12/10 , G06F12/023 , G06F12/1027 , G06F2212/657
摘要： A computer system with mechanisms for avoiding mapping conflicts in a translation look-aside buffer. A memory manager in the computer system allocates a virtual address to a process by determining a set of previously allocated virtual addresses for the process and selecting the virtual address such that the mapping of the virtual address to the translation look-aside buffer does not conflict with any of the previously allocated virtual addresses.
摘要翻译： 一种具有避免映射冲突的机制的计算机系统。 计算机系统中的存储器管理器通过确定用于该过程的先前分配的虚拟地址的集合来选择虚拟地址来分配虚拟地址，并选择虚拟地址，使得虚拟地址到翻译后备缓冲器的映射不与 任何先前分配的虚拟地址。
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公开(公告)号：US07634599B2
公开(公告)日：2009-12-15
申请号：US09895345
申请日：2001-06-29
CPC分类号： G06F13/387
摘要： A method for inline bus data compression and decompression is disclosed. In one embodiment, data is selected for transfer via a data bus, the data is divided into byte sized divisions of the bus width, and each byte is compressed by an individual compression engine. The data is then properly sequenced, aligned and recombined and further transmitted in its compressed state. When required to be decompressed, the compressed data is again divided into bytes of compressed data, each byte being decompressed individually, and then restored to the bus in its uncompressed form, in essence, in the reverse order of the compression process.
摘要翻译： 公开了一种用于内联总线数据压缩和解压缩的方法。 在一个实施例中，选择数据经由数据总线进行传输，数据被分成总线宽度的字节大小的分区，每个字节由单个压缩引擎压缩。 然后对数据进行适当排序，对齐和重新组合，并在其压缩状态下进一步传输。 当需要解压缩时，压缩数据再次被分割为压缩数据的字节，每个字节被单独解压缩，然后以其未压缩形式恢复到总线，本质上按照压缩过程的相反顺序。
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