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    Communication apparatus, phone set, communication system, communication method and communication program
    1.
    发明申请
    Communication apparatus, phone set, communication system, communication method and communication program 审中-公开
    通信设备，电话机，通信系统，通信方式和通信程序

    公开(公告)号：US20080176596A1

    公开(公告)日：2008-07-24

    申请号：US12009585

    申请日：2008-01-18

    申请人： Yongjin Jung ,  Kentaro Nakamura ,  Masafumi Matsuda ,  Masaki Kasahara ,  Kumiko Tokuhara ,  Akira Tange ,  Toru Sasaki

    发明人： Yongjin Jung ,  Kentaro Nakamura ,  Masafumi Matsuda ,  Masaki Kasahara ,  Kumiko Tokuhara ,  Akira Tange ,  Toru Sasaki

    IPC分类号： H04M1/00

    CPC分类号： H04W36/0011 ,  H04W84/12

    摘要： In the present invention, there is provided a communication apparatus including: a first communication section for a communication through a first communication path; a second communication section for a communication through a second communication path; a communication-path determination section to determine whether a present communication path currently being used is the same as a specified communication path specified as a communication path to be used, where the present communication path and the specified communication path are one of the first and second communication path, respectively; and a communication-path switching section to replace one of the first and second communication sections with the other communication section in order to replace the present communication path with the specified communication path in the course of a communication if the determination result produced by the communication-path determination section indicates that the present communication path is not the same as the specified communication path.

    摘要翻译： 在本发明中，提供了一种通信装置，包括：第一通信部，用于通过第一通信路径进行通信; 用于通过第二通信路径进行通信的第二通信部分; 确定当前正在使用的当前通信路径是否与被指定为要使用的通信路径指定的通信路径相同的通信路径确定部分，其中当前通信路径和指定的通信路径是第一和第二 通信路径分别为 以及通信路径切换部分，用于在通信过程中用另一通信部分替换第一通信部分和第二通信部分中的一个，以便在通信过程中用指定的通信路径替换当前通信路径， 路径确定部分指示当前通信路径与指定的通信路径不同。

    MOS Transistor and Semiconductor Integrated Circuit
    4.
    发明申请
    MOS Transistor and Semiconductor Integrated Circuit 有权
    MOS晶体管和半导体集成电路

    公开(公告)号：US20090166756A1

    公开(公告)日：2009-07-02

    申请号：US12336785

    申请日：2008-12-17

    申请人： Masaki Kasahara

    发明人： Masaki Kasahara

    IPC分类号： H01L29/94

    CPC分类号： H01L27/0207 ,  H01L29/1087 ,  H01L29/41758

    摘要： A MOS transistor includes plural transistor cell blocks arranged adjacently in parallel to one another, wherein the plural transistor cell blocks are configured to have plural transistor cells, plural boundaries that are parallel to the plural transistor cells, and plural back gates arranged at the plural boundaries, each of the plural transistor cell blocks has two boundaries of the plural boundaries, wherein the plural transistor cells have a substantially striped shape, and each of the plural transistor cell blocks includes: at least one drain; plural sources; and plural extended gates, wherein each of the plural transistor cells is formed from one of the plural extended gates sandwiched by one of at least one drain and one of the plural sources, one of the plural sources is adjacent to one of two boundaries, and another one of the plural sources is adjacent to another one of two boundaries.

    摘要翻译： MOS晶体管包括彼此相邻并排布置的多个晶体管单元块，其中多个晶体管单元块被配置为具有多个晶体管单元，与多个晶体管单元平行的多个边界，以及布置在多个边界的多个后栅 所述多个晶体管单元块中的每一个具有所述多个边界的两个边界，其中所述多个晶体管单元具有大致条形形状，并且所述多个晶体管单元块中的每一个包括：至少一个漏极; 复数来源 以及多个扩展栅极，其中，所述多个晶体管单元中的每一个由所述多个延伸栅极中的至少一个漏极和所述多个源中的一个形成，所述多个源极中的一个与所述多个源中的一个相邻，所述多个源中的一个与两个边界中的一个相邻， 多个来源中的另一个与两个边界中的另一个相邻。

    Domed compressed tampons
    5.
    发明授权
    Domed compressed tampons 失效

    公开(公告)号：US06299573B1

    公开(公告)日：2001-10-09

    申请号：US09369572

    申请日：1999-08-06

    申请人： Raymond J. Hull, Jr. ,  Gerd R. Rex ,  Wilfried Baer ,  Masaki Kasahara ,  Toshio Sonoda

    发明人： Raymond J. Hull, Jr. ,  Gerd R. Rex ,  Wilfried Baer ,  Masaki Kasahara ,  Toshio Sonoda

    IPC分类号： B31B100

    CPC分类号： B30B11/007 ,  A61F13/2085 ,  Y10S604/904

    摘要： An improved apparatus and method compresses a cylindrical blank into a tampon which is dimensionally stable and which is provided with a domed insertion end. A cylindrical blank is radially compressed and then introduced into a cylindrical axial compression chamber. The blank is then subjected to an extreme axial overcompression. The closed insertion end of the compression chamber has a bore formed therethrough. The bore is generally coaxial and is adapted to accept a reciprocating ejection ram having a ram surface facing into the chamber. When the ram is seated in the first position, the ram surface and the insertion end wall of the compression chamber together form a smooth doming surface. The bore periphery is of a smaller diameter than the chamber and hence radially spaced from the side walls of the chamber, and the ram has sufficient clearance to move through the chamber and eject the tampon without interference from the walls of the chamber.

    Method of preparing fine conductive pattern
    6.
    发明授权
    Method of preparing fine conductive pattern 失效
    制备精细导电图案的方法

    公开(公告)号：US5407530A

    公开(公告)日：1995-04-18

    申请号：US150405

    申请日：1993-11-10

    申请人： Shigemitsu Watanabe ,  Masaki Kasahara ,  Tadashi Ono ,  Akira Shiga ,  Tsukasa Yamada ,  Kiyohide Sakihama ,  Shin-ichi Sakaguchi ,  Masato Shimoyama

    发明人： Shigemitsu Watanabe ,  Masaki Kasahara ,  Tadashi Ono ,  Akira Shiga ,  Tsukasa Yamada ,  Kiyohide Sakihama ,  Shin-ichi Sakaguchi ,  Masato Shimoyama

    IPC分类号： C23F4/00 ,  G11B5/17 ,  G11B5/31 ,  H01L21/3205 ,  B44C1/22 ,  C03C15/00

    CPC分类号： G11B5/313 ,  G11B5/17

    摘要： An object of the invention is to provide a method of forming a fine conductive pattern. The method allows the fine conductive pattern whose thickness is relatively large to be formed easily, accurately, and surely. An insulating layer is formed on a substrate. A pattern resist is formed on the insulating layer. Then, the insulating layer is etched downward based on a profile of the pattern resist in a first etching step, and sidewalls of each of groove portions formed by the etching step of the insulating layer are etched sideways in a second etching step, so that overhang portions are defined at the lower edges of the pattern resist portions. Then, conductive film portions are formed by depositing a conductor on the pattern resist, and conductive films that are on the pattern resist are lifted off, so that a fine conductor pattern can be prepared.

    摘要翻译： 本发明的目的是提供一种形成精细导电图案的方法。 该方法允许容易，精确和可靠地形成厚度相对较大的细导电图案。 在基板上形成绝缘层。 在绝缘层上形成图案抗蚀剂。 然后，在第一蚀刻步骤中，基于图案抗蚀剂的轮廓向下蚀刻绝缘层，并且通过绝缘层的蚀刻步骤形成的每个沟槽部分的侧壁在第二蚀刻步骤中被侧向蚀刻，使得突出部 部分限定在图案抗蚀部分的下边缘处。 然后，通过在图案抗蚀剂上沉积导体来形成导电膜部分，并且剥离在图案抗蚀剂上的导电膜，从而可以制备精细的导体图案。

    MOS transistor and semiconductor integrated circuit
    7.
    发明授权
    MOS transistor and semiconductor integrated circuit 有权
    MOS晶体管和半导体集成电路

    公开(公告)号：US07847324B2

    公开(公告)日：2010-12-07

    申请号：US12336785

    申请日：2008-12-17

    申请人： Masaki Kasahara

    发明人： Masaki Kasahara

    IPC分类号： H01L29/76 ,  H01L21/70

    CPC分类号： H01L27/0207 ,  H01L29/1087 ,  H01L29/41758

    摘要： A MOS transistor includes plural transistor cell blocks arranged adjacently in parallel to one another, wherein the plural transistor cell blocks are configured to have plural transistor cells, plural boundaries that are parallel to the plural transistor cells, and plural back gates arranged at the plural boundaries, each of the plural transistor cell blocks has two boundaries of the plural boundaries, wherein the plural transistor cells have a substantially striped shape, and each of the plural transistor cell blocks includes: at least one drain; plural sources; and plural extended gates, wherein each of the plural transistor cells is formed from one of the plural extended gates sandwiched by one of at least one drain and one of the plural sources, one of the plural sources is adjacent to one of two boundaries, and another one of the plural sources is adjacent to another one of two boundaries.

    摘要翻译： MOS晶体管包括彼此相邻并排布置的多个晶体管单元块，其中多个晶体管单元块被配置为具有多个晶体管单元，与多个晶体管单元平行的多个边界，以及布置在多个边界的多个后栅 所述多个晶体管单元块中的每一个具有所述多个边界的两个边界，其中所述多个晶体管单元具有大致条形形状，并且所述多个晶体管单元块中的每一个包括：至少一个漏极; 复数来源 以及多个扩展栅极，其中，所述多个晶体管单元中的每一个由所述多个延伸栅极中的至少一个漏极和所述多个源中的一个形成，所述多个源极中的一个与所述多个源中的一个源极相邻， 多个来源中的另一个与两个边界中的另一个相邻。

    Domed compressed tampons
    8.
    发明授权
    Domed compressed tampons 失效
    圆顶压缩棉塞

    公开(公告)号：US6003216A

    公开(公告)日：1999-12-21

    申请号：US829369

    申请日：1997-03-31

    申请人： Raymond J. Hull, Jr. ,  Gerd R. Rex ,  Wilfried Baer ,  Masaki Kasahara ,  Toshio Sonoda

    发明人： Raymond J. Hull, Jr. ,  Gerd R. Rex ,  Wilfried Baer ,  Masaki Kasahara ,  Toshio Sonoda

    IPC分类号： A61F13/22 ,  A61F13/20

    CPC分类号： B30B11/007 ,  A61F13/2085 ,  Y10S604/904

    摘要： An improved apparatus and method compresses a cylindrical blank into a tampon which is dimensionally stable and which is provided with a domed insertion end. A cylindrical blank is radially compressed and then introduced into a cylindrical axial compression chamber. The blank is then subjected to an extreme axial overcompression. The closed insertion end of the compression chamber has a bore formed therethrough. The bore is generally coaxial and is adapted to accept a reciprocating ejection ram having a ram surface facing into the chamber. When the ram is seated in the first position, the ram surface and the insertion end wall of the compression chamber together form a smooth doming surface. The bore periphery is of a smaller diameter than the chamber and hence radially spaced from the side walls of the chamber, and the ram has sufficient clearance to move through the chamber and eject the tampon without interference from the walls of the chamber.

    摘要翻译： 改进的装置和方法将圆柱形坯料压缩成尺寸稳定的棉塞，并且设置有圆顶插入端。 圆柱形坯料被径向压缩，然后引入圆柱形轴向压缩室。 然后坯料经受极端的轴向过压。 压缩室的封闭插入端具有通过其形成的孔。 孔通常是同轴的，并且适于接受具有面向腔室的冲头表面的往复式排出冲头。 当冲头位于第一位置时，压头室的压头表面和插入端壁一起形成平滑的圆顶表面。 孔周边具有比腔室更小的直径，并且因此与腔室的侧壁径向间隔开，并且冲头具有足够的间隙以移动通过腔室并且弹出卫生棉条而不受室的壁的干扰。