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公开(公告)号：US07818584B1
公开(公告)日：2010-10-19
申请号：US11042937
申请日：2005-01-25
CPC分类号： G06F12/1433 , G06F21/76 , H04L9/0894 , H04L2209/12 , H04L2209/16
摘要： Circuits, methods, and apparatus that store and prevent modification or erasure of stored encoding keys, serial identification numbers, or other information. An encoding key stored with an embodiment of the present invention may be used to decode a configuration bitstream on an integrated circuit, such as an FPGA. A serial number may be used to track or authenticate an integrated circuit. Embodiments of the present invention store this information in a memory such as an SRAM, DRAM, EPROM, EEPROM, flash, fuse array, or other type of memory. In order to prevent its erasure or modification, write enable circuitry for the memory is then permanently disabled, and if the memory is volatile, a continuous power supply is provided. Further refinements verify that the write enable circuitry has been disabled before allowing the device to be configured or to be operable.
摘要翻译： 存储和防止存储的编码密钥，串行标识号或其他信息的修改或擦除的电路，方法和装置。 与本发明的实施例一起存储的编码密钥可用于解码诸如FPGA的集成电路上的配置比特流。 序列号可用于跟踪或认证集成电路。 本发明的实施例将该信息存储在诸如SRAM，DRAM，EPROM，EEPROM，闪存，熔丝阵列或其它类型的存储器之类的存储器中。 为了防止其擦除或修改，存储器的写使能电路然后被永久禁用，并且如果存储器是易失性的，则提供连续的电源。 进一步细化验证在允许设备被配置或可操作之前写使能电路已被禁用。
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公开(公告)号：US08433930B1
公开(公告)日：2013-04-30
申请号：US12884753
申请日：2010-09-17
IPC分类号： H04L29/06
CPC分类号： G06F12/1433 , G06F21/76 , H04L9/0894 , H04L2209/12 , H04L2209/16
摘要： Circuits, methods, and apparatus that store and prevent modification or erasure of stored encoding keys, serial identification numbers, or other information. An encoding key stored with an embodiment of the present invention may be used to decode a configuration bitstream on an integrated circuit, such as an FPGA. A serial number may be used to track or authenticate an integrated circuit. Embodiments of the present invention store this information in a memory such as an SRAM, DRAM, EPROM, EEPROM, flash, fuse array, or other type of memory. In order to prevent its erasure or modification, write enable circuitry for the memory is then permanently disabled, and if the memory is volatile, a continuous power supply is provided. Further refinements verify that the write enable circuitry has been disabled before allowing the device to be configured or to be operable.
摘要翻译： 存储和防止存储的编码密钥，串行识别号码或其他信息的修改或擦除的电路，方法和装置。 与本发明的实施例一起存储的编码密钥可用于解码诸如FPGA的集成电路上的配置比特流。 序列号可用于跟踪或认证集成电路。 本发明的实施例将该信息存储在诸如SRAM，DRAM，EPROM，EEPROM，闪存，熔丝阵列或其它类型的存储器之类的存储器中。 为了防止其擦除或修改，存储器的写使能电路然后被永久禁用，并且如果存储器是易失性的，则提供连续的电源。 进一步细化验证在允许设备被配置或可操作之前写使能电路已被禁用。
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公开(公告)号：US07606362B1
公开(公告)日：2009-10-20
申请号：US11042019
申请日：2005-01-25
IPC分类号： H04L21/00
CPC分类号： H04L9/0822 , H04L9/0631 , H04L9/065 , H04L9/0861 , H04L2209/24
摘要： Circuits, methods, and apparatus that prevent detection and erasure of a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a user key in order to prevent its detection. In a specific embodiment, the user key is masked by software that performs a function on it a first number of times. The result is used to encrypt a configuration bitstream. The user key is also provided to an FPGA or other device, where the function is performed a second number of times and the result stored. When the device is configured, the result is retrieved, the function is performed on it the first number of times less the second number of times and then it is used to decrypt the configuration bitstream. A further embodiment uses a one-time programmable fuse (OTP) array to prevent erasure or modification.
摘要翻译： 阻止对FPGA或其他设备的配置比特流或其他数据的检测和擦除的电路，方法和装置。 本发明的示例性实施例掩盖用户密钥以防止其检测。 在具体实施例中，用户密钥被第一次执行功能的软件掩码。 结果用于加密配置比特流。 用户密钥还提供给FPGA或其他设备，其中功能被执行第二次并且存储结果。 当配置设备时，将检索结果，该功能在其上执行第一次次数少于第二次，然后用于解密配置比特流。 另一实施例使用一次性可编程熔丝（OTP）阵列来防止擦除或修改。
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公开(公告)号：US08826038B1
公开(公告)日：2014-09-02
申请号：US13474745
申请日：2012-05-18
申请人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
发明人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
IPC分类号： G06F21/00
CPC分类号： H04L9/065 , G06F21/60 , G06F21/76 , H04L9/0877 , H04L9/14 , H04L2209/12 , H04L2209/16 , H04L2209/26
摘要： Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.
摘要翻译： 阻止检测和擦除编码或加密密钥的电路，方法和装置。 这些编码密钥可以用于对配置比特流或FPGA或其他设备的其他数据进行编码。 本发明的示例性实施例掩蔽第一密钥以形成编码密钥，以便防止第一密钥的检测。 在具体实施例中，使用第二密钥对第一密钥进行编码。 编码密钥用于对配置比特流或其他数据进行编码。 编码密钥存储在FPGA或其他设备上。 当要配置设备时，将检索编码密钥并将其用于解码比特流或其他数据。 另一实施例将加密密钥存储在一次性可编程存储器（OTP）阵列中以防止其擦除或修改。 在存储之前可以进一步模糊编码密钥。
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公开(公告)号：US08209545B1
公开(公告)日：2012-06-26
申请号：US12785400
申请日：2010-05-21
申请人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
发明人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
IPC分类号： H04L9/08
CPC分类号： H04L9/065 , G06F21/60 , G06F21/76 , H04L9/0877 , H04L9/14 , H04L2209/12 , H04L2209/16 , H04L2209/26
摘要： Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.
摘要翻译： 阻止检测和擦除编码或加密密钥的电路，方法和装置。 这些编码密钥可以用于对配置比特流或FPGA或其他设备的其他数据进行编码。 本发明的示例性实施例掩蔽第一密钥以形成编码密钥，以便防止第一密钥的检测。 在具体实施例中，使用第二密钥对第一密钥进行编码。 编码密钥用于对配置比特流或其他数据进行编码。 编码密钥存储在FPGA或其他设备上。 当要配置设备时，将检索编码密钥并将其用于解码比特流或其他数据。 另一实施例将加密密钥存储在一次性可编程存储器（OTP）阵列中以防止其擦除或修改。 在存储之前可以进一步模糊编码密钥。
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公开(公告)号：US07984292B1
公开(公告)日：2011-07-19
申请号：US12559287
申请日：2009-09-14
CPC分类号： H04L9/0822 , H04L9/0631 , H04L9/065 , H04L9/0861 , H04L2209/24
摘要： Circuits, methods, and apparatus that prevent detection and erasure of a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a user key in order to prevent its detection. In a specific embodiment, the user key is masked by software that performs a function on it a first number of times. The result is used to encrypt a configuration bitstream. The user key is also provided to an FPGA or other device, where the function is performed a second number of times and the result stored. When the device is configured, the result is retrieved, the function is performed on it the first number of times less the second number of times and then it is used to decrypt the configuration bitstream. A further embodiment uses a one-time programmable fuse (OTP) array to prevent erasure or modification.
摘要翻译： 阻止对FPGA或其他设备的配置比特流或其他数据的检测和擦除的电路，方法和装置。 本发明的示例性实施例掩盖用户密钥以防止其检测。 在具体实施例中，用户密钥被第一次执行功能的软件掩码。 结果用于加密配置比特流。 用户密钥还提供给FPGA或其他设备，其中功能被执行第二次并且存储结果。 当配置设备时，将检索结果，该功能在其上执行第一次次数少于第二次，然后用于解密配置比特流。 另一实施例使用一次性可编程熔丝（OTP）阵列来防止擦除或修改。
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公开(公告)号：US07734043B1
公开(公告)日：2010-06-08
申请号：US11042032
申请日：2005-01-25
CPC分类号： G06F21/76 , H04L9/065 , H04L9/0894 , H04L2209/12 , H04L2209/16
摘要： Circuits, methods, and apparatus that prevent easy detection and erasure or modification of an encryption or encoding key. This key may be used to encode and decode a configuration bitstream for an FPGA or other programmable or configurable device. One embodiment of the present invention obfuscates a key then stores it in a memory array on an FPGA. This memory array may be a one-time programmable memory to prevent erasure or modification of the key. After retrieval from storage, a reverse or de-obfuscation is performed to recover the key. Further obfuscation may be achieved by proper layout of the relevant circuitry.
摘要翻译： 防止容易检测和擦除或修改加密或编码密钥的电路，方法和装置。 该密钥可用于编码和解码FPGA或其他可编程或可配置设备的配置比特流。 本发明的一个实施例模糊一个密钥然后将其存储在FPGA上的存储器阵列中。 该存储器阵列可以是一次性可编程存储器，以防止键的擦除或修改。 在从存储器检索之后，执行反向或去混淆以恢复密钥。 可以通过相关电路的适当布局来实现进一步的模糊化。
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公开(公告)号：US08363833B1
公开(公告)日：2013-01-29
申请号：US13155843
申请日：2011-06-08
IPC分类号： H04L9/00
CPC分类号： H04L9/0822 , H04L9/0631 , H04L9/065 , H04L9/0861 , H04L2209/24
摘要： Circuits, methods, and apparatus that prevent detection and erasure of a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a user key in order to prevent its detection. In a specific embodiment, the user key is masked by software that performs a function on it a first number of times. The result is used to encrypt a configuration bitstream. The user key is also provided to an FPGA or other device, where the function is performed a second number of times and the result stored. When the device is configured, the result is retrieved, the function is performed on it the first number of times less the second number of times and then it is used to decrypt the configuration bitstream. A further embodiment uses a one-time programmable fuse (OTP) array to prevent erasure or modification.
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公开(公告)号：US07725738B1
公开(公告)日：2010-05-25
申请号：US11042477
申请日：2005-01-25
申请人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
发明人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
IPC分类号： G06F12/14
CPC分类号： H04L9/065 , G06F21/60 , G06F21/76 , H04L9/0877 , H04L9/14 , H04L2209/12 , H04L2209/16 , H04L2209/26
摘要： Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.
摘要翻译： 阻止检测和擦除编码或加密密钥的电路，方法和装置。 这些编码密钥可以用于对配置比特流或FPGA或其他设备的其他数据进行编码。 本发明的示例性实施例掩蔽第一密钥以形成编码密钥，以便防止第一密钥的检测。 在具体实施例中，使用第二密钥对第一密钥进行编码。 编码密钥用于对配置比特流或其他数据进行编码。 编码密钥存储在FPGA或其他设备上。 当要配置设备时，将检索编码密钥并将其用于解码比特流或其他数据。 另一实施例将加密密钥存储在一次性可编程存储器（OTP）阵列中以防止其擦除或修改。 在存储之前可以进一步模糊编码密钥。
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公开(公告)号：US08266199B2
公开(公告)日：2012-09-11
申请号：US11447472
申请日：2006-06-05
IPC分类号： G06F7/38
CPC分类号： H03K19/17732 , G06F7/527 , G06F7/5272
摘要： A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.
摘要翻译： 用于可编程逻辑器件的专用处理块包括执行两次乘法和的基本处理单元，将两个乘法的部分乘积相加，而不计算各个乘法。 这种基本处理单元消耗的面积小于传统的单独乘法器和加法器。 专用处理块还具有输入和输出级以及环回功能，以允许块被配置用于各种数字信号处理操作。
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