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1.发明授权Programmable high performance mode for multi-way associative cache/memory designs 失效可编程高性能模式，用于多路关联高速缓存/内存设计
公开(公告)号：US5778428A
公开(公告)日：1998-07-07
申请号：US577167
申请日：1995-12-22
CPC分类号： G06F12/0864 , G06F2212/1028 , Y02B60/1225
摘要： The present invention provides circuitry which facilitates user selection of alternative memory accessing techniques. The present invention provides a design approach or technique to transform the time associated with waiting for a valid "way-select" signal into cycle reduction time, thus providing a beneficial increase in the overall performance of multi-way associative cache and memory designs.
摘要翻译： 本发明提供了便于用户选择替代存储器存取技术的电路。 本发明提供了一种设计方法或技术，用于将与等待有效的“路选”信号相关联的时间转换为周期缩短时间，从而提供多路关联高速缓存和存储器设计的整体性能的有益增加。
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公开(公告)号：US5646566A
公开(公告)日：1997-07-08
申请号：US667682
申请日：1996-06-21
CPC分类号： H03K3/356156 , H03K3/012
摘要： A dynamic latch circuit design minimizes set and restore power without sacrificing speed. The dynamic latch circuit provides two significant power saving advantages over traditional dynamic latch designs. The first regulates dynamic restore power with the state of the latch. If the dynamic internal node of the latch has not been discharged, then the restore signal applied to the input of the latch is not transferred to the restore device attached to the node. By isolating the restore device under these conditions, additional power is not wasted boot-strapping up the already precharged node. Second, by design, the restore path and set path are separate. The input signals used to set the latch are different and isolated from those performing the restore. Therefore, there is no conducting path between the voltage source and circuit ground as the restore device turns on.
摘要翻译： 动态锁存电路设计可最大限度地降低设置和恢复功耗，而不会牺牲速度。 与传统的动态锁存器设计相比，动态锁存电路提供了两个显着的省电优势。 第一个调节动态恢复功率与锁存器的状态。 如果锁存器的动态内部节点未放电，则施加到锁存器输入端的恢复信号不会传送到连接到该节点的恢复设备。 通过在这些条件下隔离恢复设备，额外的电源不会浪费已经预充电节点的引导。 第二，按设计，恢复路径和设置路径是分开的。 用于设置锁存器的输入信号是不同的，与执行恢复的输入信号隔离。 因此，当恢复装置打开时，电压源和电路地之间没有导通路径。
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3.发明授权Programmable pulsewidth and delay generating circuit for integrated circuits 有权用于集成电路的可编程脉冲宽度和延迟发生电路公开(公告)号：US07869302B2
公开(公告)日：2011-01-11
申请号：US12543256
申请日：2009-08-18
IPC分类号： G11C8/00
CPC分类号： G11C11/413 , G11C11/41 , G11C29/12015 , G11C29/50 , G11C29/50012 , G11C2029/1202 , G11C2029/1208 , H03K5/06 , H03K5/13 , H03K5/1565
摘要： A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.
摘要翻译： 本地片上可编程脉冲宽度和延迟产生电路包括被配置为接收全局时钟信号并输出本地时钟信号的时钟产生电路。 时钟产生电路包括脉冲整形部分，其根据后沿延迟和前沿延迟中的至少一个调整全局时钟信号的脉冲宽度。 前沿延迟由前沿延迟电路产生，并且后沿延迟由后沿延迟电路产生，后沿延迟电路被配置为对脉冲的后沿施加延迟。 后沿延迟电路包括具有可编程级的延迟元件的延迟链，每个级都使用从地址锁存器解码的控制位独立控制。
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4.发明申请公开(公告)号：US20080310246A1
公开(公告)日：2008-12-18
申请号：US11761655
申请日：2007-06-12
CPC分类号： G11C11/413 , G11C11/41 , G11C29/12015 , G11C29/50 , G11C29/50012 , G11C2029/1202 , G11C2029/1208 , H03K5/06 , H03K5/13 , H03K5/1565
摘要： A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.
摘要翻译： 本地片上可编程脉冲宽度和延迟产生电路包括被配置为接收全局时钟信号并输出本地时钟信号的时钟产生电路。 时钟产生电路包括脉冲整形部分，其根据后沿延迟和前沿延迟中的至少一个调整全局时钟信号的脉冲宽度。 前沿延迟由前沿延迟电路产生，并且后沿延迟由后沿延迟电路产生，后沿延迟电路被配置为对脉冲的后沿施加延迟。 后沿延迟电路包括具有可编程级的延迟元件的延迟链，每个级都使用从地址锁存器解码的控制位独立控制。
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5.发明申请METHOD AND APPARATUS FOR CALIBRATING INTERNAL PULSES IN AN INTEGRATED CIRCUIT 有权用于在集成电路中校准内部脉冲的方法和装置公开(公告)号：US20080309364A1
公开(公告)日：2008-12-18
申请号：US11761610
申请日：2007-06-12
IPC分类号： G01R31/02
CPC分类号： G01R31/31725 , G01R31/31726
摘要： A method and circuit for measuring internal pulses includes an enable circuit configured to receive a control signal from an on-chip built-in tester to enable measurement of internal circuits. A delay chain is configured to receive a pulse signal from an on-chip circuit component. Sampling latches each include a data input coupled between adjacent delay elements of the delay chain and synchronized with the clock signal such that a transition in the pulse signal is indicated by comparing adjacent digital values in an output sequence.
摘要翻译： 用于测量内部脉冲的方法和电路包括使能电路，其被配置为从片上内置测试器接收控制信号以使得能够测量内部电路。 延迟链被配置为从片上电路部件接收脉冲信号。 采样锁存器各自包括耦合在延迟链的相邻延迟元件之间并与时钟信号同步的数据输入，使得通过比较输出序列中的相邻数字值来指示脉冲信号中的转变。
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公开(公告)号：US07117400B2
公开(公告)日：2006-10-03
申请号：US10065723
申请日：2002-11-13
IPC分类号： G06F11/20 , G11C11/4094 , G11C15/00 , G11C15/04
CPC分类号： G11C29/832 , G11C15/00 , G11C29/848
摘要： An integrated circuit including: a set of bitlines; a set of data lines; means for coupling each respective data line to a first respective bitline or to a second respective bitline based on a steering signal, the second respective bitline being adjacent to the first respective bitline; and means for maintaining the first respective bitline at a desired potential after the data line is coupled to the second bitline.
摘要翻译： 一种集成电路，包括：一组位线; 一组数据线; 用于基于转向信号将每个相应数据线耦合到第一相应位线或第二相应位线的装置，所述第二相应位线与所述第一相应位线相邻; 以及用于在数据线耦合到第二位线之后将第一相应位线保持在期望电位的装置。
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公开(公告)号：US08744731B2
公开(公告)日：2014-06-03
申请号：US13292472
申请日：2011-11-09
申请人： Dan Wertz , Kevin A. Batson , Dae Kon Yi , Sean Lavin , Paul Cappa
发明人： Dan Wertz , Kevin A. Batson , Dae Kon Yi , Sean Lavin , Paul Cappa
CPC分类号： F02D31/001 , F02D29/06 , F02D41/28
摘要： An electronic digital governor assembly includes a case, a printed circuit board housed within said case, the printed circuit board having control circuitry configured for controlling at least one parameter of an energy production device, and a user interface including a digital display for displaying a value of the at least one parameter and at least one button for selectively adjusting the value.
摘要翻译： 电子数字调速器组件包括壳体，容纳在所述壳体内的印刷电路板，所述印刷电路板具有被配置为用于控制能量产生装置的至少一个参数的控制电路，以及包括用于显示值的数字显示器的用户界面 的至少一个参数和用于选择性地调整该值的至少一个按钮。
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公开(公告)号：US20120123664A1
公开(公告)日：2012-05-17
申请号：US13292472
申请日：2011-11-09
申请人： Dan Wertz , Kevin A. Batson , Dae Kon Yi , Sean Lavin , Paul Cappa
发明人： Dan Wertz , Kevin A. Batson , Dae Kon Yi , Sean Lavin , Paul Cappa
CPC分类号： F02D31/001 , F02D29/06 , F02D41/28
摘要： An electronic digital governor assembly includes a case, a printed circuit board housed within said case, the printed circuit board having control circuitry configured for controlling at least one parameter of an energy production device, and a user interface including a digital display for displaying a value of the at least one parameter and at least one button for selectively adjusting the value.
摘要翻译： 电子数字调速器组件包括壳体，容纳在所述壳体内的印刷电路板，所述印刷电路板具有被配置为用于控制能量产生装置的至少一个参数的控制电路，以及包括用于显示值的数字显示器的用户界面 的至少一个参数和用于选择性地调整该值的至少一个按钮。
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公开(公告)号：US07944229B2
公开(公告)日：2011-05-17
申请号：US12543215
申请日：2009-08-18
IPC分类号： G01R31/02
CPC分类号： G01R31/31725 , G01R31/31726
摘要： A method and circuit for measuring internal pulses includes an enable circuit configured to receive a control signal from an on-chip built-in tester to enable measurement of internal circuits. A delay chain is configured to receive a pulse signal from an on-chip circuit component. Sampling latches each include a data input coupled between adjacent delay elements of the delay chain and synchronized with the clock signal such that a transition in the pulse signal is indicated by comparing adjacent digital values in an output sequence.
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10.发明授权System and method for conserving power in a content addressable memory by providing an independent search line voltage 有权通过提供独立的搜索线电压来节省内容可寻址存储器中的功率的系统和方法公开(公告)号：US06442055B1
公开(公告)日：2002-08-27
申请号：US10016025
申请日：2001-12-12
申请人： Robert E. Busch , Kevin A. Batson
发明人： Robert E. Busch , Kevin A. Batson
IPC分类号： G11C1500
CPC分类号： G11C15/043 , G11C15/04
摘要： A system and method is disclosed for operating a content addressable memory (CAM) within an integrated circuit using search signals at search input voltages which are substantially independent from an operating voltage of the CAM. A method is disclosed in which search signals are input to CAM cells of the CAM at search input voltages which are substantially independent of an operating voltage of storage elements within the CAM cells. A match signal is output upon detecting a matching condition between the search signals and data stored in the storage elements. The search input voltage can be within about 0.2V above a threshold voltage of a search input device of the CAM memory cell. Search input devices can be selected to have a lower threshold voltage than other devices included within the CAM cell.
摘要翻译： 公开了一种用于在搜索输入电压下使用基本上独立于CAM的工作电压的搜索信号来操作集成电路内的内容可寻址存储器（CAM）的系统和方法。 公开了一种方法，其中搜索信号以基本上独立于CAM单元内的存储元件的工作电压的搜索输入电压输入到CAM的CAM单元。 在检测到搜索信号和存储在存储元件中的数据之间的匹配条件时输出匹配信号。 搜索输入电压可以在CAM存储器单元的搜索输入装置的阈值电压以上约0.2V内。 可以选择搜索输入设备以具有比包括在CAM单元内的其它设备更低的阈值电压。
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