公开(公告)号：US07634708B2

公开(公告)日：2009-12-15

申请号：US11532294

申请日：2006-09-15

申请人： Kevin W. Kark ,  Liyong Wang ,  Carl B. Ford, III ,  Pak-kin Mak

发明人： Kevin W. Kark ,  Liyong Wang ,  Carl B. Ford, III ,  Pak-kin Mak

IPC分类号： G06F11/00

CPC分类号： G06F12/1475 ,  G06F11/08

摘要： Storage protection keys and system data share the same physical storage. The key region is dynamically relocatable by firmware. A Configuration Array is used to map the absolute address of the key region in to its physical address. The absolute address of keys can be fixed even though the physical location of the keys is relocated into a different region. A triple-detect double correct ECC scheme is used to protect keys. The ECC scheme is different from regular data in the storage and can be used to detect illegal access. Extra firmware and hardware is also designed to restrain customer's applications from directly accessing keys. With the key region being relocatable, the firmware could move the key region away from a known faulty area in a memory to improve system RAS. We also achieved the commonality objective that key memory device can use the same memory devices with other server systems that do not use keys.

摘要翻译： 存储保护密钥和系统数据共享相同的物理存储。 关键区域是通过固件动态重新定位。 配置阵列用于将关键区域的绝对地址映射到其物理地址。 即使键的物理位置被重新定位到不同的区域，键的绝对地址也可以被固定。 三重检测双正确ECC方案用于保护密钥。 ECC方案与存储中的常规数据不同，可用于检测非法访问。 额外的固件和硬件也旨在限制客户的应用程序直接访问密钥。 在可重新定位关键区域的情况下，固件可以将密钥区域从存储器中的已知故障区域移开，以改善系统RAS。 我们还实现了共同目标，即密钥存储设备可以与不使用密钥的其他服务器系统使用相同的存储设备。

公开(公告)号：US07590899B2

公开(公告)日：2009-09-15

申请号：US11532267

申请日：2006-09-15

申请人： Donald J. Swietek ,  Bruce G. Hazelzet ,  Roger A. Rippens ,  Carl B. Ford, III ,  Kevin W. Kark ,  Pak-kin Mak ,  Liyong Wang

发明人： Donald J. Swietek ,  Bruce G. Hazelzet ,  Roger A. Rippens ,  Carl B. Ford, III ,  Kevin W. Kark ,  Pak-kin Mak ,  Liyong Wang

IPC分类号： G11C29/00 ,  G06F11/00 ,  G06F13/00

CPC分类号： G06F12/1416

摘要： A DDR SDRAM DIMM for a mainframe main storage subsystem has a plurality of DDR SDRAMs on a rectangular printed circuit board having a first side and a second side, a length (152 MM=6 inch) between 149 and 153 millimeters and optimized at 149.15 mm or 151.35 mm in length and first and second ends having a width smaller than the length; a first plurality of connector locations on the first side extending along a first edge of the board that extends the length of the board, a second plurality of connector locations of the second side extending on the first edge of the board, a locating key having its center positioned on the first edge and located between 80 mm and 86 mm and optimized with a locating key 1.5 mm wide centered at 81.58 or 85.67 mm from the first end of the board and located between 64 and 70 mm and optimized with the locating key centered at 67.58 or 65.675 from the second end of the board. Each DIMM has memory regions comprising one of a plurality of physical entities hereafter referred to as memory macros which are relocatable regions which contain SP Keys and data set storage in the DIMM physical memory. These memory macros SP Key regions define an arbitrary logic structure for main storage which has a hard physical boundary.

摘要翻译： 用于主机主存储子系统的DDR SDRAM DIMM具有在具有第一侧和第二侧的矩形印刷电路板上的多个DDR SDRAM，长度（152MM = 6英寸）在149和153毫米之间，并且在149.15mm处优化 或151.35mm的长度，第一和第二端的宽度小于长度; 所述第一侧的第一多个连接器位置沿所述板的第一边缘延伸，所述第一边延伸所述板的长度，所述第二侧的第二多个连接器位置在所述板的第一边缘上延伸，定位键具有其 中心位于第一个边缘，位于80 mm和86 mm之间，并使用1.5 mm宽的定位键进行优化，定位键距离板的第一端81.58或85.67 mm，位于64至70 mm之间，并以定位键为中心进行优化 从板的第二端67.58或65.675。 每个DIMM具有包括以下称为存储宏的多个物理实体中的一个的存储器区域，其是在DIMM物理存储器中包含SP密钥和数据集存储的可重定位区域。 这些内存宏SP键区域为主存储器定义了一个具有硬物理边界的任意逻辑结构。

公开(公告)号：US20080072109A1

公开(公告)日：2008-03-20

申请号：US11532267

申请日：2006-09-15

申请人： Donald J. Swietek ,  Bruce G. Hazelzet ,  Roger A. Rippens ,  Carl B. Ford ,  Kevin W. Kark ,  Pak-kin Mak ,  Liyong Wang

发明人： Donald J. Swietek ,  Bruce G. Hazelzet ,  Roger A. Rippens ,  Carl B. Ford ,  Kevin W. Kark ,  Pak-kin Mak ,  Liyong Wang

IPC分类号： G06F12/16 ,  G06F11/07 ,  G06F11/22

CPC分类号： G06F12/1416

摘要： A DDR SDRAM DIMM for a mainframe main storage subsystem has a plurality of DDR SDRAMs on a rectangular printed circuit board having a first side and a second side, a length (152 MM=6 inch) between 149 and 153 millimeters and optimized at 149.15 mm or 151.35 mm in length and first and second ends having a width smaller than the length; a first plurality of connector locations on the first side extending along a first edge of the board that extends the length of the board, a second plurality of connector locations of the second side extending on the first edge of the board, a locating key having its center positioned on the first edge and located between 80 mm and 86 mm and optimized with a locating key 1.5 mm wide centered at 81.58 or 85.67 mm from the first end of the board and located between 64 and 70 mm and optimized with the locating key centered at 67.58 or 65.675 from the second end of the board. Each DIMM has memory regions comprising one of a plurality of physical entities hereafter referred to as memory macros which are relocatable regions which contain SP Keys and data set storage in the DIMM physical memory. These memory macros SP Key regions define an arbitrary logic structure for main storage which has a hard physical boundary.

摘要翻译： 用于主机主存储子系统的DDR SDRAM DIMM具有在具有第一侧和第二侧的矩形印刷电路板上的多个DDR SDRAM，长度（152MM = 6英寸）在149和153毫米之间，并且在149.15mm处优化 或151.35mm的长度，第一和第二端的宽度小于长度; 所述第一侧的第一多个连接器位置沿所述板的第一边缘延伸，所述第一边延伸所述板的长度，所述第二侧的第二多个连接器位置在所述板的第一边缘上延伸，定位键具有其 中心位于第一个边缘，位于80 mm和86 mm之间，并使用1.5 mm宽的定位键进行优化，定位键距离板的第一端81.58或85.67 mm，位于64至70 mm之间，并以定位键为中心进行优化 从板的第二端67.58或65.675。 每个DIMM具有包括以下称为存储宏的多个物理实体中的一个的存储器区域，其是在DIMM物理存储器中包含SP密钥和数据集存储的可重定位区域。 这些内存宏SP键区域为主存储器定义了一个具有硬物理边界的任意逻辑结构。

公开(公告)号：US20080071964A1

公开(公告)日：2008-03-20

申请号：US11532294

申请日：2006-09-15

申请人： Kevin W. Kark ,  Liyong Wang ,  Carl B. Ford ,  Pak-kin Mak

发明人： Kevin W. Kark ,  Liyong Wang ,  Carl B. Ford ,  Pak-kin Mak

IPC分类号： G06F12/14

CPC分类号： G06F12/1475 ,  G06F11/08

摘要： Storage protection keys and system data share the same physical storage. The key region is dynamically relocatable by firmware. A Configuration Array is used to map the absolute address of the key region in to its physical address. The absolute address of keys can be fixed even though the physical location of the keys is relocated into a different region. A triple-etect double correct ECC scheme is used to protect keys. The ECC scheme is different from regular data in the storage and can be used to detect illegal access. Extra firmware and hardware is also designed to restrain customer's applications from directly accessing keys. With the key region being relocatable, the firmware could move the key region away from a known faulty area in a memory to improve system RAS. We also achieved the commonality objective that key memory device can use the same memory devices with other server systems that do not use keys.

摘要翻译： 存储保护密钥和系统数据共享相同的物理存储。 关键区域是通过固件动态重新定位。 配置阵列用于将关键区域的绝对地址映射到其物理地址。 即使键的物理位置被重新定位到不同的区域，键的绝对地址也可以被固定。 使用三重等效双重ECC方案来保护密钥。 ECC方案与存储中的常规数据不同，可用于检测非法访问。 额外的固件和硬件也旨在限制客户的应用程序直接访问密钥。 在可重新定位关键区域的情况下，固件可以将密钥区域从存储器中的已知故障区域移开，以改善系统RAS。 我们还实现了共同目标，即密钥存储设备可以与不使用密钥的其他服务器系统使用相同的存储设备。

公开(公告)号：US07739526B2

公开(公告)日：2010-06-15

申请号：US11934799

申请日：2007-11-05

申请人： Kevin W. Kark ,  Liyong Wang

发明人： Kevin W. Kark ,  Liyong Wang

IPC分类号： G06F1/00

CPC分类号： G06F1/26 ,  G11C5/14 ,  G11C11/4074

摘要： A method for regulating system power using a power governor for DRAM in a multi-node computer system regulating memory power consumption of an entire computer system employs a closed ring that connects all the power governors within the system to enable them to work in concert so that each of the power governors has the knowledge of memory activities within the entire system. They then control and limit the memory usage based on a true overall measurement instead of just local measurement. Each nodal power governor has memory command counter, ring number receiver, ring number transmitter, governor activation controller, and memory traffic controller. Each nodal power governor counts the weight of memory command. The degree of limiting actual memory activities can be programmed when the governor is active. Besides, the command priorities can be adjusted in activation too. A hybrid ring structure can be employed with a nodal power structure to achieve the fastest number circulation speed economically.

摘要翻译： 在调节整个计算机系统的存储器功耗的多节点计算机系统中使用用于DRAM的功率调节器来调节系统功率的方法采用闭环，其连接系统内的所有功率调节器，使得它们能够一致地工作，使得 每个功率调节器都具有整个系统内的记忆活动知识。 然后，它们基于真正的总体测量来控制和限制内存使用，而不仅仅是本地测量。 每个节点功率调节器具有存储器命令计数器，振铃号接收器，振铃号发射器，调速器激活控制器和存储器流量控制器。 每个节点功率调节器计算存储器命令的权重。 当调速器处于活动状态时，可以编程限制实际记忆活动的程度。 此外，命令优先级也可以在激活中进行调整。 可以采用具有节点功率结构的混合环结构以经济地实现最快的数量循环速度。

公开(公告)号：US20070283104A1

公开(公告)日：2007-12-06

申请号：US11421167

申请日：2006-05-31

申请人： George C. Wellwood ,  Liyong Wang ,  Kevin W. Kark

发明人： George C. Wellwood ,  Liyong Wang ,  Kevin W. Kark

IPC分类号： G06F13/00

CPC分类号： G06F11/106 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0409

摘要： Disclosed are a concurrent selftest engine and its applications to verify, initialize and scramble the system memory concurrently along with mainline operations. In prior art, memory reconfiguration and initialization can only be done by firmware with a full system shutdown and reboot. The disclosed hardware, working along with firmware, allows us to do comprehensive memory test operations on the extended customer memory area while the customer mainline memory accesses arc running in parallel. The hardware consists of concurrent selftest engines and priority logic. Great flexibility is achieved by the new design because customer-usable memory area can be dynamically allocated, verified and initialized. The system performance is improved by the fact that the selftest is hardware-driven whereas in prior art, the firmware drove the selftest. More comprehensive test patterns can be used to improve system memory RAS as well.

摘要翻译： 公开了一种并发的最佳引擎及其应用程序，用于与主线操作同时验证，初始化和加扰系统内存。 在现有技术中，内存重新配置和初始化只能通过完全系统关机和重新启动的固件来完成。 所公开的硬件与固件一起使用，使我们能够在扩展的客户内存区域进行全面的内存测试操作，同时客户主线内存访问并行运行。 硬件由并发的最佳引擎和优先级逻辑组成。 新设计实现了极大的灵活性，因为可以动态分配，验证和初始化客户可用的内存区域。 系统性能由于以下事实而得到改善，即：selftest是硬件驱动的，而在现有技术中，固件驱动的是最新的。 更全面的测试模式也可用于改进系统内存RAS。

公开(公告)号：US06898725B2

公开(公告)日：2005-05-24

申请号：US10108100

申请日：2002-03-27

申请人： Kevin W. Kark ,  Liyong Wang

发明人： Kevin W. Kark ,  Liyong Wang

IPC分类号： G06F1/04 ,  G06F1/12

CPC分类号： G06F1/04

摘要： Disclosed is a method and a computer circuit design for a dynamic clock ratio detector. The detector is used to determine the ratio between two clock domains. The detector has a driver 101 and a receiver, which reside in different clock domains. The driver 101 constantly produces a ratio clock pulse to the receiver. The ratio-counter in the receiver counts the pulse width based on its local clock cycles. The clock ratio detector has many features, including absorbing the meta-stability effect when the pulse crosses an asynchronous interface. The clock ratio detector prevents output counts oscillation, provides an adjustable ratio-detecting coverage range, a programmable system-parameter generator 104, and a programmable error reporter 105.

摘要翻译： 公开了一种用于动态时钟比率检测器的方法和计算机电路设计。 检测器用于确定两个时钟域之间的比率。 检测器具有位于不同时钟域中的驱动器101和接收器。 驱动器101不断地向接收器产生比率时钟脉冲。 接收器中的比例计数器根据其本地时钟周期对脉冲宽度进行计数。 时钟比率检测器具有许多特征，包括当脉冲穿过异步接口时吸收元稳定性效应。 时钟比率检测器防止输出计数振荡，提供可调整的比率检测覆盖范围，可编程系统参数发生器104和可编程误差报告器105。

公开(公告)号：US07917777B2

公开(公告)日：2011-03-29

申请号：US11937980

申请日：2007-11-09

申请人： Liyong Wang ,  Kevin W. Kark

发明人： Liyong Wang ,  Kevin W. Kark

IPC分类号： G06F1/00

CPC分类号： G06F1/32

摘要： A method of regulating power for multi-node computer system components has a closed-ring path that links all the power governors and circulating in the ring is a system power number that represents the power consumption of the entire system. Meanwhile, all the governors keep counting its local power consumption. Each time the number passes a governor, the governor will add its local count onto this number, store this number for future usage, and reset its local count. When the new number returns back to the same power governor, the governor will subtract the new number with its stored number to calculate the overall system power usage within a number circulation period. The system power number overflow problem is also detected with a counter if the incoming number is smaller then the number previously stored. The counter whose counting capacity is greater than the maximum system power usage on all the nodes within a number circulation period. A single number transfer mode and multiple number transfer mode and heterogeneous multi-node components which could have different power usage configurations are employed.

摘要翻译： 调节多节点计算机系统组件功率的方法具有连接所有功率调节器的闭环路径，并且在环路中循环是表示整个系统的功耗的系统功率数。 同时，所有的省长都不断地计算当地的电力消耗。 每当该号码通过州长时，州长会将其本地计数添加到该号码上，存储此号码以供将来使用，并重置其本地计数。 当新号码返回相同的调速器时，总监将以其存储号码减去新号码，以计算数字循环期间的整体系统功率使用情况。 如果输入的数字小于先前存储的数字，则也会使用计数器检测系统电源数量溢出问题。 计数器的计数能力大于数字循环周期内所有节点的最大系统功耗。 采用可以具有不同功率使用配置的单个传输模式和多个传输模式和异构多节点组件。

公开(公告)号：US07340619B2

公开(公告)日：2008-03-04

申请号：US11082123

申请日：2005-03-16

申请人： Liyong Wang ,  Kevin W. Kark

发明人： Liyong Wang ,  Kevin W. Kark

IPC分类号： G06F1/00

CPC分类号： G06F1/32

摘要： A method of regulating power for multi-node computer system components has a closed-ring path that links all the power governors and circulating in the ring is a system power number that represents the power consumption of the entire system. Meanwhile, all the governors keep counting its local power consumption. Each time the number passes a governor, the governor will add its local count onto this number, store this number for future usage, and reset its local count. When the new number returns back to the same power governor, the governor will subtract the new number with its stored number to calculate the overall system power usage within a number circulation period. The system power number overflow problem is also detected with a counter if the incoming number is smaller then the number previously stored. The counter whose counting capacity is greater than the maximum system power usage on all the nodes within a number circulation period. A single number transfer mode and multiple number transfer mode and heterogeneous multi-node components which could have different power usage configurations are employed.

摘要翻译： 调节多节点计算机系统组件功率的方法具有连接所有功率调节器的闭环路径，并且在环路中循环是表示整个系统的功耗的系统功率数。 同时，所有的省长都不断地计算当地的电力消耗。 每当该号码通过州长时，州长会将其本地计数添加到该号码上，存储此号码以供将来使用，并重置其本地计数。 当新号码返回相同的调速器时，总监将以其存储号码减去新号码，以计算数字循环期间的整体系统功率使用情况。 如果输入的数字小于先前存储的数字，则也会使用计数器检测系统电源数量溢出问题。 计数器的计数能力大于数字循环周期内所有节点的最大系统功耗。 采用可以具有不同功率使用配置的单个传输模式和多个传输模式和异构多节点组件。

公开(公告)号：US07340618B2

公开(公告)日：2008-03-04

申请号：US11081115

申请日：2005-03-16

申请人： Kevin W. Kark ,  Liyong Wang

发明人： Kevin W. Kark ,  Liyong Wang

IPC分类号： G06F1/00

CPC分类号： G06F1/26 ,  G11C5/14 ,  G11C11/4074

摘要： A power governor for DRAM in a multi-node computer system regulating memory power consumption of an entire computer system employs a closed ring that connects all the power governors within the system to enable them to work in concert so that each of the power governors has the knowledge of memory activities within the entire system. They then control and limit the memory usage based on a true overall measurement instead of just local measurement. Each nodal power governor has memory command counter, ring number receiver, ring number transmitter, governor activation controller, and memory traffic controller. Each nodal power governor counts the weight of memory command. The degree of limiting actual memory activities can be programmed when the governor is active. Besides, the command priorities can be adjusted in activation too. A hybrid ring structure can be employed with a nodal power structure to achieve the fastest number circulation speed economically.

摘要翻译： 在调节整个计算机系统的存储器功耗的多节点计算机系统中的用于DRAM的功率调节器采用闭环，其连接系统内的所有功率调节器，使得它们能够协调工作，使得每个功率调节器具有 知识在整个系统内的记忆活动。 然后，它们基于真正的总体测量来控制和限制内存使用，而不仅仅是本地测量。 每个节点功率调节器具有存储器命令计数器，振铃号接收器，振铃号发射器，调速器激活控制器和存储器流量控制器。 每个节点功率调节器计算存储器命令的权重。 当调速器处于活动状态时，可以编程限制实际记忆活动的程度。 此外，命令优先级也可以在激活中进行调整。 可以采用具有节点功率结构的混合环结构以经济地实现最快的数量循环速度。