摘要:
In one aspect, the present invention provides a latch/ejector face plate assembly for an end of an electronics chassis assembly. The face plate is pivotally couplable to a front end of an electronics chassis. The face plate has a latch/ejector that comprises a latching portion that is latchably engageable against a rear side of a latching/fulcrum flange of a electronics rack shelf when the face plate is in a closed position, and an ejector edge that is engageable against a front side of the latching/fulcrum flange when the face plate is in an open position, to thereby provide an ejection force of the electronics chassis.
摘要:
In one aspect, the present invention provides a latch/ejector face plate assembly for an end of an electronics chassis assembly. The face plate is pivotally couplable to a front end of an electronics chassis. The face plate has a latch/ejector that comprises a latching portion that is latchably engageable against a rear side of a latching/fulcrum flange of a electronics rack shelf when the face plate is in a closed position, and an ejector edge that is engageable against a front side of the latching/fulcrum flange when the face plate is in an open position, to thereby provide an ejection force of the electronics chassis.
摘要:
Advertisement quality measures (e.g., predicted click through rates) are modified in accordance with a user's preferences with respect to domains to which the advertisements relate.
摘要:
A planar electronic device includes top conductors on a top side of a planar substrate connected to conductive vias and defining top conductor groups and bottom conductors on a bottom side connected to corresponding vias and defining bottom conductor groups. The conductors and vias define primary and secondary conductive loops with the top conductor group including at least one primary top conductor and at least one secondary top conductor and with the bottom conductor group including at least one primary bottom conductor and at least one secondary bottom conductor. The top conductors within each group have substantially similar layouts that are different from layouts of the immediately adjacent groups, and the bottom conductors within each group have substantially similar layouts that are different from layouts of the immediately adjacent groups.
摘要:
A multilayer inductor device includes a planar substrate, a ferrite body, and an outer and an inner conductive coil. The substrate includes plural dielectric layers with the ferrite body is disposed in the substrate. The outer and inner conductive coils are helically wrapped around the ferrite body. The outer conductive coil includes first upper conductors, first lower conductors, and first conductive vias vertically extending through the substrate and conductively coupled with the first upper and lower conductors. The inner conductive coil includes second upper conductors, second lower conductors, and second conductive vias vertically extending through the substrate and conductively coupled with the second upper and lower conductors. The inner conductive coil is disposed between the outer conductive coil and the ferrite body.
摘要:
An arrangement for clamping a flat plate to a flat surface includes juxtaposing the plate to the flat surface. An axially-movable wedging element defining a surface fitted with wedges is fixed against motion in other than a direction of elongation, and is forced to move in the direction of elongation. The wedges are forced against a first spring beam to impart forces thereto. The forces are coupled from the first spring beam to a second spring beam by intermediary supports. The second spring beam bears against a surface of the flat plate to force the plate against the flat surface.
摘要:
For testing a device under test (“DUT”) a test specification is converted in a computer system by a pin vector generator process, which includes generating test vectors. The DUT has numerous input pins and such a pin vector is for a signal to drive one such pin. The pin vectors are compressed and saved. Ones of the pin vectors are loaded, upon initialization of a test, into a pipeline having a series of memory stages and extending from the computer system to channel cards in a test head. The pipeline is operated in data transfer cycles, delivering W bits per cycle. The pin vectors are decompressed at the respective channel cards in decompressor read cycles. X bits are read per decompressor cycle, W being greater than X, so that the pipeline may perform its data transfer cycles less frequently than the decompressor performs its read cycles.
摘要:
Aspects for notched gate structure fabrication are described. The notched gate fabrication includes forming spacers of hard mask material on a gate conductor, and utilizing the spacers during etching to form notches in the gate conductor and provide a notched gate structure. In a further aspect, notched gate fabrication includes performing a timed etch of masked gate conductive material to maintain a portion of a gate conductive layer and provide gate structure areas in the gate conductive layer. Anisotropically etching the gate structure areas provides spacers on the gate structure areas. Isotropically etching the portion of the gate conductive layer provides notched gates in the gate structure areas.
摘要:
An apparatus for holding a cover in a closed orientation substantially covering a chassis face of a unit; the unit containing equipment in an equipment volume; the equipment volume being partially bounded by the chassis face; includes: a positioning structure coupling the cover with the unit for selectively situating the cover in the closed orientation or in an other orientation; and a latching structure configured for latchingly engaging the chassis face and the cover for holding the cover in the closed orientation when the latching structure is in a first orientation. The latching structure does not engage the chassis face and the cover when the latching structure is in a second orientation. The latching structure is situated substantially entirely outside the equipment volume.
摘要:
A multilayer inductor device includes a planar substrate, a ferrite body, and an outer and an inner conductive coil. The substrate includes plural dielectric layers with the ferrite body is disposed in the substrate. The outer and inner conductive coils are helically wrapped around the ferrite body. The outer conductive coil includes first upper conductors, first lower conductors, and first conductive vias vertically extending through the substrate and conductively coupled with the first upper and lower conductors. The inner conductive coil includes second upper conductors, second lower conductors, and second conductive vias vertically extending through the substrate and conductively coupled with the second upper and lower conductors. The inner conductive coil is disposed between the outer conductive coil and the ferrite body.