公开(公告)号：US08730402B2

公开(公告)日：2014-05-20

申请号：US13450035

申请日：2012-04-18

申请人： Sang Ho Kim ,  Ho Jin Park ,  Hyung Woan Koo ,  Ki Ho Lee

发明人： Sang Ho Kim ,  Ho Jin Park ,  Hyung Woan Koo ,  Ki Ho Lee

IPC分类号： H04N5/455

CPC分类号： H04N21/42607 ,  H04N5/14 ,  H04N5/455 ,  H04N5/46 ,  H04N5/50 ,  H04N5/60 ,  H04N21/42638 ,  H04N21/42676 ,  H04N21/439

摘要： Provided is an analog front end of a digital TV, a digital TV system having the same, and a method of operating the same. The analog front end includes: a first selection circuit which selectively outputs differential sound intermediate frequency signals or differential TV broadcast signals in response to a first selection signal; a second selection circuit which outputs a clock signal among a plurality of clock signals having a different sampling frequencies, in response to a second selection signal; and an analog-to-digital converter which converts output signals output from the first selection circuit to a digital code, according to a sampling frequency of a clock signal output from the second selection circuit.

摘要翻译： 提供了数字电视的模拟前端，具有该数字电视的数字电视系统及其操作方法。 模拟前端包括：第一选择电路，其响应于第一选择信号选择性地输出差分声音中频信号或差分TV广播信号; 第二选择电路，响应于第二选择信号，在具有不同采样频率的多个时钟信号中输出时钟信号; 以及根据从第二选择电路输出的时钟信号的采样频率，将从第一选择电路输出的输出信号转换为数字码的模数转换器。

公开(公告)号：US09628671B2

公开(公告)日：2017-04-18

申请号：US13713051

申请日：2012-12-13

申请人： Ki Ho Lee ,  Hyung Woan Koo ,  Sang Ho Kim ,  Ho Jin Park

发明人： Ki Ho Lee ,  Hyung Woan Koo ,  Sang Ho Kim ,  Ho Jin Park

IPC分类号： H03L7/00 ,  H04N5/06 ,  H04N5/44 ,  H04N5/46 ,  H04N21/43

CPC分类号： H04N5/06 ,  H04N5/4401 ,  H04N5/46 ,  H04N21/4305

摘要： The front-end integrated circuit includes a first clock unit receiving a reference clock signal from an oscillator and generating a first clock signal, a first analog front end module receiving and processing a first broadcast signal using the first clock signal, a second clock unit receiving the reference clock signal and generating a second clock signal, and a second analog front end module receiving and processing a second broadcast signal using the second clock signal.

公开(公告)号：US20130169870A1

公开(公告)日：2013-07-04

申请号：US13713051

申请日：2012-12-13

申请人： Ki Ho Lee ,  Hyung Woan Koo ,  Sang Ho Kim ,  Ho Jin Park

发明人： Ki Ho Lee ,  Hyung Woan Koo ,  Sang Ho Kim ,  Ho Jin Park

IPC分类号： H04N5/06

CPC分类号： H04N5/06 ,  H04N5/4401 ,  H04N5/46 ,  H04N21/4305

摘要： The front-end integrated circuit includes a first clock unit receiving a reference clock signal from an oscillator and generating a first clock signal, a first analog front end module receiving and processing a first broadcast signal using the first clock signal, a second clock unit receiving the reference clock signal and generating a second clock signal, and a second analog front end module receiving and processing a second broadcast signal using the second clock signal.

摘要翻译： 前端集成电路包括：第一时钟单元，接收来自振荡器的参考时钟信号并产生第一时钟信号，第一模拟前端模块使用第一时钟信号接收和处理第一广播信号;第二时钟单元接收 参考时钟信号并产生第二时钟信号，以及第二模拟前端模块，使用第二时钟信号接收和处理第二广播信号。