公开(公告)号：US09166034B2

公开(公告)日：2015-10-20

申请号：US13948629

申请日：2013-07-23

申请人： Ki-hyung Nam ,  Pulunsol Cho ,  Yong Kwan Kim

发明人： Ki-hyung Nam ,  Pulunsol Cho ,  Yong Kwan Kim

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L27/22 ,  H01L27/24 ,  H01L27/108 ,  H01L45/00

CPC分类号： H01L21/76224 ,  H01L21/823481 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/78 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

摘要： A semiconductor device, and a method of fabricating the same, include a substrate including two-dimensionally arranged active portions, device isolation patterns extending along sidewalls of the active portions, each of the device isolation patterns including first and second device isolation patterns, gate patterns extending across the active portions and the device isolation patterns, each of the gate patterns including a gate insulating layer, a gate line and a gate capping pattern, and ohmic patterns on the active portions, respectively. Top surfaces of the first device isolation pattern and the gate insulating layer may be lower than those of the second device isolation pattern and the gate capping pattern, respectively, and the ohmic patterns may include an extending portion on the first insulating layer.

摘要翻译： 半导体器件及其制造方法包括：包括二维布置的有源部分的器件隔离图案，沿着有源部分的侧壁延伸的器件隔离图案，每个器件隔离图案包括第一和第二器件隔离图案，栅极图案 延伸穿过有源部分和器件隔离图案，每个栅极图案分别包括栅极绝缘层，栅极线和栅极覆盖图案以及有源部分上的欧姆图案。 第一器件隔离图案和栅极绝缘层的顶表面可以分别低于第二器件隔离图案和栅极封盖图案的表面，并且欧姆图案可以包括在第一绝缘层上的延伸部分。

公开(公告)号：US09287160B2

公开(公告)日：2016-03-15

申请号：US14826758

申请日：2015-08-14

申请人： Ki-hyung Nam ,  Pulunsol Cho ,  Yong Kwan Kim

发明人： Ki-hyung Nam ,  Pulunsol Cho ,  Yong Kwan Kim

IPC分类号： H01L27/088 ,  H01L21/762 ,  H01L21/8234

CPC分类号： H01L21/76224 ,  H01L21/823481 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/78 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

摘要： A semiconductor device, and a method of fabricating the same, include a substrate including two-dimensionally arranged active portions, device isolation patterns extending along sidewalls of the active portions, each of the device isolation patterns including first and second device isolation patterns, gate patterns extending across the active portions and the device isolation patterns, each of the gate patterns including a gate insulating layer, a gate line and a gate capping pattern, and ohmic patterns on the active portions, respectively. Top surfaces of the first device isolation pattern and the gate insulating layer may be lower than those of the second device isolation pattern and the gate capping pattern, respectively, and the ohmic patterns may include an extending portion on the first insulating layer.

公开(公告)号：US08901526B2

公开(公告)日：2014-12-02

申请号：US13753712

申请日：2013-01-30

申请人： Ki-hyung Nam ,  Yong-kwan Kim ,  Ho-joong Lee ,  Pulunsol Cho

发明人： Ki-hyung Nam ,  Yong-kwan Kim ,  Ho-joong Lee ,  Pulunsol Cho

IPC分类号： H01L29/00 ,  H01L45/00 ,  H01L27/22

CPC分类号： H01L45/1253 ,  H01L27/228

摘要： A variable resistive memory device capable of reducing contact resistance by including a contact layer having low contact resistance, the variable resistive memory device including a substrate comprising an active region; a gate line on the substrate; a first contact layer electrically connected to the active region; a memory cell contact plug electrically connected to the first contact layer; and a variable resistive memory cell electrically connected to the memory cell contact plug, wherein the first contact layer has less contact resistance with respect to the active region than the memory cell contact plug.

摘要翻译： 一种可变电阻存储器件，其能够通过包括具有低接触电阻的接触层来降低接触电阻，所述可变电阻式存储器件包括包括有源区的衬底; 衬底上的栅极线; 电连接到有源区的第一接触层; 电连接到所述第一接触层的存储单元接触插塞; 以及电连接到所述存储单元接触插塞的可变电阻存储单元，其中所述第一接触层相对于所述有源区具有比所述存储单元接触插塞更小的接触电阻。