公开(公告)号：US6025267A

公开(公告)日：2000-02-15

申请号：US115724

申请日：1998-07-15

申请人： Kin-Leong Pey ,  Soh-Yun Siah ,  Yong-Meng Lee

发明人： Kin-Leong Pey ,  Soh-Yun Siah ,  Yong-Meng Lee

IPC分类号： H01L21/285 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/46

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/32134

摘要： A method for forming self-aligned, metal silicide, (salicide), layers, on polysilicon gate structures, and on source/drain regions, located in a first region of a semiconductor substrate, while avoiding the salicide formation, on polysilicon gate structures, and on source/drain regions, located in a second region of a semiconductor substrate, has been developed. A composite insulator shape, comprising an overlying silicon nitride layer, and an underlying TEOS deposited, silicon oxide layer, is used to block polysilicon, as well as silicon regions, in the second region of the semiconductor substrate, from salicide formation. Unwanted silicon oxide spacers, created on the sides of polysilicon gate structures, during the patterning of the composite insulator shape, is selectively removed using dilute hydrofluoric acid solutions.

摘要翻译： 一种在多晶硅栅结构上形成位于半导体衬底的第一区域中的自对准金属硅化物，（硅化物）层，多晶硅栅极结构上的源极/漏极区域，同时避免形成硅化物的方法， 并且已经开发了位于半导体衬底的第二区域中的源极/漏极区域上。 使用包括上覆氮化硅层和下面的TEOS沉积的氧化硅层的复合绝缘体形状来阻挡半导体衬底的第二区域中的多晶硅以及硅区域，从硅化物形成。 使用稀氢氟酸溶液选择性地去除在复合绝缘体形状的图案化期间在多晶硅栅极结构的侧面上产生的不需要的氧化硅间隔物。

公开(公告)号：US08623714B2

公开(公告)日：2014-01-07

申请号：US12728488

申请日：2010-03-22

申请人： Jae-Eun Park ,  Weipeng Li ,  Deleep R. Nair ,  M. Dean Sciacca ,  Voon-Yew Thean ,  Ava Wan ,  Dong-Hun Lee ,  Yong-Meng Lee

发明人： Jae-Eun Park ,  Weipeng Li ,  Deleep R. Nair ,  M. Dean Sciacca ,  Voon-Yew Thean ,  Ava Wan ,  Dong-Hun Lee ,  Yong-Meng Lee

IPC分类号： H01L21/00

CPC分类号： H01L29/7833 ,  H01L21/28518 ,  H01L21/76895 ,  H01L29/665 ,  H01L29/6659

摘要： The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.

摘要翻译： 本公开提供了形成电气装置的方法。 该方法可以从衬底上形成栅极结构开始，其中间隔物直接与栅极结构的侧壁接触。 源极区和漏极区形成在衬底中。 在栅极结构上形成金属半导体合金，间隔物的外侧壁和源极区域和漏极区域中的一个。 在金属半导体合金上形成层间电介质层。 通过金属半导体合金上的层间电介质停止形成通孔。 在通孔中的金属半导体合金形成互连。 本公开还包括通过上述方法制造的结构。

公开(公告)号：US20110227136A1

公开(公告)日：2011-09-22

申请号：US12728488

申请日：2010-03-22

申请人： Jae-Eun Park ,  Weipeng Li ,  Deleep R. Nair ,  M. Dean Sciacca ,  Voon-Yew Thean ,  Ava Wan ,  Dong-Hun Lee ,  Yong-Meng Lee

发明人： Jae-Eun Park ,  Weipeng Li ,  Deleep R. Nair ,  M. Dean Sciacca ,  Voon-Yew Thean ,  Ava Wan ,  Dong-Hun Lee ,  Yong-Meng Lee

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/28518 ,  H01L21/76895 ,  H01L29/665 ,  H01L29/6659

摘要： The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.

摘要翻译： 本公开提供了形成电气装置的方法。 该方法可以从衬底上形成栅极结构开始，其中间隔物直接与栅极结构的侧壁接触。 源极区和漏极区形成在衬底中。 在栅极结构上形成金属半导体合金，间隔物的外侧壁和源极区域和漏极区域中的一个。 在金属半导体合金上形成层间电介质层。 通过金属半导体合金上的层间电介质停止形成通孔。 在通孔中的金属半导体合金形成互连。 本公开还包括通过上述方法制造的结构。