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    Spacer protection and electrical connection for array device
    1.
    发明授权
    Spacer protection and electrical connection for array device 失效
    阵列器件的间隔保护和电气连接

    公开(公告)号：US08623714B2

    公开(公告)日：2014-01-07

    申请号：US12728488

    申请日：2010-03-22

    申请人： Jae-Eun Park ,  Weipeng Li ,  Deleep R. Nair ,  M. Dean Sciacca ,  Voon-Yew Thean ,  Ava Wan ,  Dong-Hun Lee ,  Yong-Meng Lee

    发明人： Jae-Eun Park ,  Weipeng Li ,  Deleep R. Nair ,  M. Dean Sciacca ,  Voon-Yew Thean ,  Ava Wan ,  Dong-Hun Lee ,  Yong-Meng Lee

    IPC分类号： H01L21/00

    CPC分类号： H01L29/7833 ,  H01L21/28518 ,  H01L21/76895 ,  H01L29/665 ,  H01L29/6659

    摘要： The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.

    摘要翻译： 本公开提供了形成电气装置的方法。 该方法可以从衬底上形成栅极结构开始，其中间隔物直接与栅极结构的侧壁接触。 源极区和漏极区形成在衬底中。 在栅极结构上形成金属半导体合金，间隔物的外侧壁和源极区域和漏极区域中的一个。 在金属半导体合金上形成层间电介质层。 通过金属半导体合金上的层间电介质停止形成通孔。 在通孔中的金属半导体合金形成互连。 本公开还包括通过上述方法制造的结构。

    SPACER PROTECTION AND ELECTRICAL CONNECTION FOR ARRAY DEVICE
    2.
    发明申请
    SPACER PROTECTION AND ELECTRICAL CONNECTION FOR ARRAY DEVICE 失效
    阵列保护和电气连接

    公开(公告)号：US20110227136A1

    公开(公告)日：2011-09-22

    申请号：US12728488

    申请日：2010-03-22

    申请人： Jae-Eun Park ,  Weipeng Li ,  Deleep R. Nair ,  M. Dean Sciacca ,  Voon-Yew Thean ,  Ava Wan ,  Dong-Hun Lee ,  Yong-Meng Lee

    发明人： Jae-Eun Park ,  Weipeng Li ,  Deleep R. Nair ,  M. Dean Sciacca ,  Voon-Yew Thean ,  Ava Wan ,  Dong-Hun Lee ,  Yong-Meng Lee

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7833 ,  H01L21/28518 ,  H01L21/76895 ,  H01L29/665 ,  H01L29/6659

    摘要： The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.

    摘要翻译： 本公开提供了形成电气装置的方法。 该方法可以从衬底上形成栅极结构开始，其中间隔物直接与栅极结构的侧壁接触。 源极区和漏极区形成在衬底中。 在栅极结构上形成金属半导体合金，间隔物的外侧壁和源极区域和漏极区域中的一个。 在金属半导体合金上形成层间电介质层。 通过金属半导体合金上的层间电介质停止形成通孔。 在通孔中的金属半导体合金形成互连。 本公开还包括通过上述方法制造的结构。

    INTEGRATED CIRCUIT STRUCTURE HAVING SUBSTANTIALLY PLANAR N-P STEP HEIGHT AND METHODS OF FORMING
    3.
    发明申请
    INTEGRATED CIRCUIT STRUCTURE HAVING SUBSTANTIALLY PLANAR N-P STEP HEIGHT AND METHODS OF FORMING 失效
    具有大面积平面N-P步高的集成电路结构及其形成方法

    公开(公告)号：US20120256268A1

    公开(公告)日：2012-10-11

    申请号：US13083631

    申请日：2011-04-11

    申请人： Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Voon-Yew Thean ,  Young Way Teh

    发明人： Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Voon-Yew Thean ,  Young Way Teh

    IPC分类号： H01L27/092 ,  H01L21/304 ,  H01L21/20

    CPC分类号： H01L21/823878 ,  H01L21/76232 ,  H01L21/823807

    摘要： Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.

    摘要翻译： 公开了用于形成具有基本平坦的N-P台阶高度的集成电路结构的解决方案。 在一个实施例中，一种方法包括：提供具有n型场效应晶体管（NFET）区和p型场效应晶体管（PFET）区的结构; 在PFET区域上形成掩模以使NFET区域露出; 在暴露的NFET区域上进行稀释的氟化氢（DHF）清洁以显着降低NFET区域的STI分布; 以及在执行DHF之后在PFET区域中形成硅锗（SiGE）通道。

    Integrated circuit structure having substantially planar N-P step height and methods of forming
    4.
    发明授权
    Integrated circuit structure having substantially planar N-P step height and methods of forming 失效
    具有基本上平面的N-P台阶高度的集成电路结构和形成方法

    公开(公告)号：US08563394B2

    公开(公告)日：2013-10-22

    申请号：US13083631

    申请日：2011-04-11

    申请人： Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Voon-Yew Thean ,  Young Way Teh

    发明人： Weipeng Li ,  Deleep R. Nair ,  Jae-Eun Park ,  Voon-Yew Thean ,  Young Way Teh

    IPC分类号： H01L21/76

    CPC分类号： H01L21/823878 ,  H01L21/76232 ,  H01L21/823807

    摘要： Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.

    摘要翻译： 公开了用于形成具有基本平坦的N-P台阶高度的集成电路结构的解决方案。 在一个实施例中，一种方法包括：提供具有n型场效应晶体管（NFET）区域和p型场效应晶体管（PFET）区域的结构; 在PFET区域上形成掩模以使NFET区域露出; 在暴露的NFET区域上进行稀释的氟化氢（DHF）清洁以显着降低NFET区域的STI分布; 以及在执行DHF之后在PFET区域中形成硅锗（SiGE）通道。

    Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors
    9.
    发明授权
    Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors 失效
    紧凑型器件/电路/芯片泄漏电流（IDDQ）计算，包括工艺引起的隆起因素

    公开(公告)号：US08626480B2

    公开(公告)日：2014-01-07

    申请号：US12574440

    申请日：2009-10-06

    申请人： Paul Chang ,  Jie Deng ,  Terrence B. Hook ,  Sim Y. Loo ,  Anda C. Mocuta ,  Jae-Eun Park ,  Kern Rim ,  Xiaojun Yu

    发明人： Paul Chang ,  Jie Deng ,  Terrence B. Hook ,  Sim Y. Loo ,  Anda C. Mocuta ,  Jae-Eun Park ,  Kern Rim ,  Xiaojun Yu

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G01R31/2848 ,  G01R31/3008 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5036

    摘要： A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.

    摘要翻译： 一种用于将静态电流泄漏特定模型实现为半导体器件设计和电路设计流程的系统，方法和计算机程序产品。 泄漏模型涵盖宽温度和电压范围的所有器件几何，并且不需要堆叠因子计算，也不需要基于平板的IDDQ计算。 IDDQ计算的泄漏模型包含进一步的寄生和邻近效应。 泄漏模型在不同的测试水平下实施泄漏计算，例如从单个设备到全芯片设计，并且集成在一个单一的模型中。 泄漏模型通过单个开关设置的杠杆来实现不同测试级别的泄漏计算。 该实现是通过硬件定义语言代码或面向对象的代码，其可以使用感兴趣的网表来编译和操作，例如用于进行性能分析。