公开(公告)号：US06230226B1

公开(公告)日：2001-05-08

申请号：US08940540

申请日：1997-09-30

申请人： King Seng Hu ,  Vui Yong Liew ,  Bruce Moore ,  Thomas Ohe

发明人： King Seng Hu ,  Vui Yong Liew ,  Bruce Moore ,  Thomas Ohe

IPC分类号： G06F1300

CPC分类号： G06F13/4022

摘要： A system and apparatus combining a hub and a function as a single chip compound device. A single serial interface engine (SIE) is shared between a hub endpoint and a function endpoint. The hub endpoint and function endpoint being integrated on a single chip. A single backend interface is coupled between the SIE and the endpoints. The backend interface selects which of the hub endpoints or the function endpoints can access the shared SIE at any time period. In one embodiment, a first address is associated with the hub and a second address is associated with the function. The backend interface selects between the hub and function by comparing a translated address received from the SIE with each of the first address and the second address. The result of the comparisons via suitable combinational logic serves as a select signal for a multiplexer between the hub/function and the SIE.

摘要翻译： 将集线器和功能组合为单芯片复合器件的系统和装置。 单个串行接口引擎（SIE）在集线器端点和功能端点之间共享。 集线器端点和功能端点集成在单个芯片上。 单个后端接口连接在SIE和端点之间。 后端接口选择哪个集线器端点或功能端点可以在任何时间段访问共享SIE。 在一个实施例中，第一地址与集线器相关联，并且第二地址与该功能相关联。 后端接口通过将从SIE接收的转换地址与第一地址和第二地址中的每一个进行比较，在集线器和功能之间进行选择。 通过适当的组合逻辑进行比较的结果可作为集线器/功能与SIE之间的多路复用器的选择信号。

公开(公告)号：US5652894A

公开(公告)日：1997-07-29

申请号：US536087

申请日：1995-09-29

申请人： King Seng Hu ,  Vui Yong Liew

发明人： King Seng Hu ,  Vui Yong Liew

IPC分类号： G06F11/14 ,  G06F1/32

CPC分类号： G06F9/4418 ,  Y02B60/186

摘要： A clock and reset unit for providing power saving modes to a pipelined microprocessor and for guaranteeing that power saving instruction is the last to be executed before the clocks stop, upon wake-up the next instruction executed is the first instruction in the interrupt service routine (ISR) and that upon return from the ISR, the instruction immediately following the power saving instruction is executed. A register is provided in the clock and reset unit for initiating a power saving mode. A software programmer selects a particular power saving mode by setting a corresponding bit in this register (i.e., writing a predetermined value to this register). A processor stalling signal generator for generating a signal that indicates to the processor that the peripheral is not ready to process a processor request (thereby causing the processor to insert wait states until the peripheral is ready) is provided. The clock and reset unit is also provided a signal from an interrupt handler indicating that the processor will be executing the ISR upon leaving the power save instruction. In response to this signal, the clock and reset unit de-assert the wait state request and brought the processor out of the power saving instruction.

摘要翻译： 一种时钟和复位单元，用于向流水线微处理器提供省电模式，并且用于保证在停止时钟之前最后执行的省电指令，在唤醒时，执行的下一指令是中断服务程序中的第一条指令（ ISR），并且从ISR返回时，执行紧接在省电指令之后的指令。 在时钟和复位单元中提供一个寄存器，用于启动省电模式。 软件编程器通过在该寄存器中设置相应的位（即向该寄存器写入预定值）来选择特定的省电模式。 一种处理器停止信号发生器，用于产生一个信号，该信号向处理器指示外围设备未准备好处理处理器请求（从而使处理器插入等待状态，直到外设准备就绪）。 时钟和复位单元还提供来自中断处理器的信号，指示处理器在离开省电指令时将执行ISR。 响应该信号，时钟和复位单元解除等待状态请求，并使处理器退出省电指令。

公开(公告)号：US5822595A

公开(公告)日：1998-10-13

申请号：US581463

申请日：1995-12-29

申请人： King Seng Hu

发明人： King Seng Hu

IPC分类号： G06F13/24 ,  G06F13/32

CPC分类号： G06F13/24 ,  G06F13/32

摘要： An interrupt handler unit (IHU) for polling and arbitrating among interrupt sources and for generating a request for interrupt to a processor if winning priority is higher than an in-progress priority. The interrupt handler unit, upon acknowledgment by the processor, generates a vector address on an interface bus and at the same time pushes an acknowledged priority onto an in-progress priority (IPP) stack. The interrupt acknowledge is then provided to the appropriate interrupt source for the source to clear a pending flag. Upon a return from interrupt (RETI) instruction, the in-progress priority (IPP) stack is popped by the interrupt handler unit. The interrupt channels are time multiplexed based on interrupt state signals, and the individual interrupt sources can be masked. Interrupt related registers, (such as enable, priority, and flag) reside in the interrupt handler unit. The priority of an individual interrupt source is programmable using an interrupt priority registers, which are also provided in the IHU.

摘要翻译： 中断处理单元（IHU），用于在中断源之间轮询和仲裁，并且如果获胜优先级高于正在进行的优先级，则产生对处理器的中断请求。 中断处理单元经处理器确认后，在接口总线上生成向量地址，同时将确认的优先级推送到正在进行中的优先级（IPP）堆栈。 然后将中断确认提供给适当的中断源，以清除源代码。 在从中断（RETI）指令返回时，中断优先级（IPP）堆栈由中断处理单元弹出。 中断通道基于中断状态信号进行时间复用，各个中断源可以被屏蔽。 中断相关寄存器（如使能，优先级和标志）驻留在中断处理单元中。 单个中断源的优先级可以使用IHU中提供的中断优先级寄存器进行编程。