公开(公告)号：US11942176B2

公开(公告)日：2024-03-26

申请号：US17475482

申请日：2021-09-15

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki ,  Xu Li ,  Masayuki Miura ,  Takayuki Miyazaki ,  Toshio Fujisawa ,  Hiroto Nakai ,  Hideko Mukaida ,  Mie Matsuo

IPC: G11C5/00 ,  G11C5/14 ,  G11C16/30 ,  H02M3/158 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C5/14 ,  G11C16/30 ,  H02M3/1582 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.

公开(公告)号：US11568901B2

公开(公告)日：2023-01-31

申请号：US17470955

申请日：2021-09-09

Applicant: Kioxia Corporation

Inventor： Kazushige Kawasaki ,  Masayuki Miura ,  Hideko Mukaida

IPC: G11C5/06 ,  H01L23/10

Abstract: A semiconductor device of an embodiment includes: a wiring board having a first surface and a second surface on a side opposite to the first surface; a first semiconductor element on the first surface of the wiring board; a second semiconductor element on the first surface of the wiring board; and a first sealing material that seals at least the second semiconductor element. A slit is formed in the first sealing material between the first semiconductor element and the second semiconductor element. When a thickness of the first sealing material on the first semiconductor element is t1 and a thickness of the first sealing material on the second semiconductor element is t2, the t1 and the t2 satisfy a relationship of 0≤t1

公开(公告)号：US12224236B2

公开(公告)日：2025-02-11

申请号：US17460468

申请日：2021-08-30

Applicant: Kioxia Corporation

Inventor： Hideo Aoki ,  Hideko Mukaida ,  Satoshi Tsukiyama

IPC: H01L23/498 ,  H01L25/18

Abstract: A semiconductor device according to an embodiment includes a substrate and a semiconductor chip. The semiconductor chip is provided over the substrate. The substrate includes a wire layer and an insulating layer. The wire layer includes a wire electrically connected to the semiconductor chip. The insulating layer is provided in contact with the wire layer and includes a glass woven fabric containing a resin. The glass woven fabric includes a plurality of glass fibers that are provided along two or more directions parallel with the glass woven fabric and are woven. The glass fibers differ in at least one of the material, number, and thickness depending on the directions parallel with the glass woven fabric.