公开(公告)号：US20220077286A1

公开(公告)日：2022-03-10

申请号：US17350492

申请日：2021-06-17

Applicant: Kioxia Corporation

Inventor： Tomonari SHIODA ,  Yasunori OSHIMA ,  Taichi IWASAKI ,  Shota YAMAGIWA ,  Hiroto SAITO

IPC: H01L29/08 ,  H01L29/417 ,  H01L27/12 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device in an embodiment includes a substrate and a transistor. The transistor includes a source layer, a drain layer, a gate insulation film, a gate electrode, a contact plug and a first epitaxial layer. The source layer and the drain layer are provided in surface regions of the substrate, and contain an impurity. The gate insulation film is provided on the substrate between the source layer and the drain layer. The gate electrode is provided on the gate insulation film. The contact plug is provided so as to protrude to the source layer or the drain layer downward of a surface of the substrate. The first epitaxial layer is provided between the contact plug and the source layer or drain layer, and contains both the impurity and carbon.

公开(公告)号：US20240188310A1

公开(公告)日：2024-06-06

申请号：US18453919

申请日：2023-08-22

Applicant: Kioxia Corporation

Inventor： Hiroto SAITO

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: According to one embodiment, a semiconductor memory device includes a first chip and a second chip contacting the first chip. The second chip includes a memory cell array. First bonding pads are on the first chip. Second bonding pads are on the second chip and contact the first bonding pads. A first electrode pad is in a first plane parallel with the first bonding pads. A second electrode pad is in a second plane with the second bonding pads. A first insulator layer is interposed between the first electrode pad and the second electrode pad.