公开(公告)号：US20230178491A1

公开(公告)日：2023-06-08

申请号：US17895377

申请日：2022-08-25

Applicant: KIOXIA CORPORATION

Inventor： Yasuo TAKEMOTO ,  Hitoshi ISHII ,  Masayuki MIURA

IPC: H01L23/538 ,  H01L23/528 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/5384 ,  H01L23/528 ,  H01L23/562 ,  H01L23/49816 ,  H01L23/3121 ,  H01L24/05 ,  H01L25/0657 ,  H01L24/16 ,  H01L2224/05541 ,  H01L2224/16151

Abstract: A semiconductor device includes: a printed wiring substrate; a semiconductor chip mounted on a first surface of the printed wiring substrate; a sealing resin sealing the semiconductor chip on the first surface of the printed wiring substrate; an electrode pad provided on a second surface on a side opposite to the first surface of the printed wiring substrate; an electrode terminal connected to the electrode pad and protruding from the second surface; and a metal layer provided on a surface of the electrode pad on the electrode terminal side or on the side opposite to the electrode terminal so as to straddle a boundary line of the bonding surface between the electrode terminal and the electrode pad which is at least a boundary line on a side facing an outside of a mounting region of the semiconductor chip.

公开(公告)号：US20210287992A1

公开(公告)日：2021-09-16

申请号：US17004244

申请日：2020-08-27

Applicant: Kioxia Corporation

Inventor： Hitoshi ISHII

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor device having a substrate, a semiconductor chip, and a plurality of electrode terminals is provided. The substrate has first and second principal surfaces. The semiconductor chip is disposed on the first principal surface. The electrode terminals are disposed on the second principal surface. The substrate has a via interconnection near a position at which an outer edge line of the semiconductor chip intersects an outer outline of the electrode terminal farthest from a center of the substrate, the electrode terminal farthest from the center of the substrate being among the plurality of electrode terminals overlapping the outer edge line in a predetermined condition as seen through the substrate of the semiconductor device from a direction perpendicular to the first principal surface, the via interconnection connecting a first interconnection layer on a first principal surface-side to a second interconnection layer on a second principal surface-side.