公开(公告)号：US20240105681A1

公开(公告)日：2024-03-28

申请号：US18458023

申请日：2023-08-29

Applicant: Kioxia Corporation

Inventor： Satoru ITAKURA ,  Masayuki MIURA

IPC: H01L25/065 ,  H01L21/027 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L25/0657 ,  H01L21/0274 ,  H01L21/56 ,  H01L23/293 ,  H01L2225/06506

Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes placing a first semiconductor element on a wiring board, forming a first mask having an opening on the wiring board so that the first semiconductor element is positioned in the opening, putting a liquid first resin precursor into the opening of the first mask, curing the first resin precursor to obtain a first resin layer, and then removing the first mask.

公开(公告)号：US20230207520A1

公开(公告)日：2023-06-29

申请号：US17934135

申请日：2022-09-21

Applicant: Kioxia Corporation

Inventor： Masayuki MIURA ,  Kazuma HASEGAWA ,  Kazushige KAWASAKI

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L24/48 ,  H01L24/32 ,  H01L24/73 ,  H01L2924/1438 ,  H01L2924/1431 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48149 ,  H01L2224/48225 ,  H01L2924/182 ,  H01L21/563

Abstract: A semiconductor device includes a wiring substrate inside which a wiring layer is provided, a plurality of first semiconductor chips stacked in a shifted manner on the wiring substrate and each provided with a connection terminal on a surface facing the wiring substrate, and a second semiconductor chip having a function different from functions of the first semiconductor chips and provided on the wiring substrate on a side where the connection terminals are electrically connected to the wiring substrate.

公开(公告)号：US20230178491A1

公开(公告)日：2023-06-08

申请号：US17895377

申请日：2022-08-25

Applicant: KIOXIA CORPORATION

Inventor： Yasuo TAKEMOTO ,  Hitoshi ISHII ,  Masayuki MIURA

IPC: H01L23/538 ,  H01L23/528 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/5384 ,  H01L23/528 ,  H01L23/562 ,  H01L23/49816 ,  H01L23/3121 ,  H01L24/05 ,  H01L25/0657 ,  H01L24/16 ,  H01L2224/05541 ,  H01L2224/16151

Abstract: A semiconductor device includes: a printed wiring substrate; a semiconductor chip mounted on a first surface of the printed wiring substrate; a sealing resin sealing the semiconductor chip on the first surface of the printed wiring substrate; an electrode pad provided on a second surface on a side opposite to the first surface of the printed wiring substrate; an electrode terminal connected to the electrode pad and protruding from the second surface; and a metal layer provided on a surface of the electrode pad on the electrode terminal side or on the side opposite to the electrode terminal so as to straddle a boundary line of the bonding surface between the electrode terminal and the electrode pad which is at least a boundary line on a side facing an outside of a mounting region of the semiconductor chip.

公开(公告)号：US20240421121A1

公开(公告)日：2024-12-19

申请号：US18734204

申请日：2024-06-05

Applicant: Kioxia Corporation

Inventor： Masayuki MIURA ,  Kazuma HASEGAWA ,  Hideko MUKAIDA ,  Kana KUDO

IPC: H01L25/065 ,  H10B80/00

Abstract: A semiconductor device according to an embodiment includes a substrate, a first stack, a second stack, a first bonding layer, a second bonding layer, a first wire, and a second wire. The first stack has a plurality of first semiconductor chips. The second stack has a plurality of second semiconductor chips. The first bonding layer is provided at a lower part of each of the plurality of first semiconductor chips. The second bonding layer is provided at a lower part of each of the plurality of second semiconductor chips. The first wire electrically connects the first semiconductor chips and the second semiconductor chips to one another. The second wire electrically connects the substrate and the second semiconductor chips. The first bonding layer provided at the lower part of the first semiconductor chip in a lowest stage has a thickness different from the thickness of the other first bonding layers.

公开(公告)号：US20230411366A1

公开(公告)日：2023-12-21

申请号：US18336626

申请日：2023-06-16

Applicant: Kioxia Corporation

Inventor： Masayuki MIURA

IPC: H01L25/16 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L25/16 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H10B80/00 ,  H01L2224/48265 ,  H01L2224/49109 ,  H01L2224/48225 ,  H01L2224/49052 ,  H01L2225/06562 ,  H01L2225/0651 ,  H01L2225/06506

Abstract: A semiconductor device according to the present disclosure includes: a semiconductor chip including a first supply terminal and a second supply terminal; a passive element provided on the semiconductor chip, the passive element including a first electrode, a dielectric provided on the first electrode, and a second electrode provided on the dielectric; a first wiring which electrically connects the first supply terminal and the first electrode to each other; and a second wiring which electrically connects the second supply terminal and the second electrode to each other.

公开(公告)号：US20220293138A1

公开(公告)日：2022-09-15

申请号：US17470955

申请日：2021-09-09

Applicant: Kioxia Corporation

Inventor： Kazushige KAWASAKI ,  Masayuki MIURA ,  Hideko MUKAIDA

IPC: G11C5/06 ,  H01L23/10

Abstract: A semiconductor device of an embodiment includes: a wiring board having a first surface and a second surface on a side opposite to the first surface; a first semiconductor element on the first surface of the wiring board; a second semiconductor element on the first surface of the wiring board; and a first sealing material that seals at least the second semiconductor element. A slit is formed in the first sealing material between the first semiconductor element and the second semiconductor element. When a thickness of the first sealing material on the first semiconductor element is t1 and a thickness of the first sealing material on the second semiconductor element is t2, the t1 and the t2 satisfy a relationship of 0≤t1

公开(公告)号：US20220223552A1

公开(公告)日：2022-07-14

申请号：US17695654

申请日：2022-03-15

Applicant: Kioxia Corporation

Inventor： Yasuhito YOSHIMIZU ,  Takashi FUKUSHIMA ,  Tatsuro HITOMI ,  Arata INOUE ,  Masayuki MIURA ,  Shinichi KANNO ,  Toshio FUJISAWA ,  Keisuke NAKATSUKA ,  Tomoya SANUKI

IPC: H01L23/00 ,  H01L23/544 ,  G06F11/07

Abstract: A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.

公开(公告)号：US20220285320A1

公开(公告)日：2022-09-08

申请号：US17459866

申请日：2021-08-27

Applicant: Kioxia Corporation

Inventor： Yuichi SANO ,  Masayuki MIURA ,  Kazuma HASEGAWA

IPC: H01L25/065 ,  H01L23/00 ,  H01L29/417

Abstract: A semiconductor device includes a first stacked body including a plurality of first semiconductor chips stacked along a first direction, each of the first semiconductor chips being offset from the other first semiconductor chips along a second direction perpendicular to the first direction; a first columnar electrode connected to an electrode pad of the first stacked body, and extending in the first direction; a second stacked body including a plurality of second semiconductor chips stacked along the first direction, each of the second semiconductor chips being offset from the other second semiconductor chips along the second direction, the second stacked body having a height larger than the first stacked body and overlap at least a portion of the first stacked body when viewed from the top; and a second columnar electrode connected to an electrode pad of the second stacked body, and extending in the first direction.

公开(公告)号：US20220204270A1

公开(公告)日：2022-06-30

申请号：US17694532

申请日：2022-03-14

Applicant: Kioxia Corporation

Inventor： Yasuhito YOSHIMIZU ,  Takashi FUKUSHIMA ,  Tatsuro HITOMI ,  Arata INOUE ,  Masayuki MIURA ,  Shinichi KANNO ,  Toshio FUJISAWA ,  Keisuke NAKATSUKA ,  Tomoya SANUKI

IPC: B65G1/137

Abstract: According to one embodiment, a storage device includes a control apparatus and a stocker. The control apparatus writes data to or reads data from a storage medium that includes a plurality of non-volatile memory chips. The stocker stores a plurality of the storage media that are detached from the control apparatus. The control apparatus includes a first temperature control system. The first temperature control system raises temperature of the storage medium to a first temperature or higher. The stocker includes a second temperature control system. The second temperature control system cools the storage medium to a second temperature or lower. The second temperature is lower than the first temperature.

公开(公告)号：US20210149568A1

公开(公告)日：2021-05-20

申请号：US17121024

申请日：2020-12-14

Applicant: Kioxia Corporation

Inventor： Yasuhito YOSHIMIZU ,  Takashi FUKUSHIMA ,  Tatsuro HITOMI ,  Arata INOUE ,  Masayuki MIURA ,  Shinichi KANNO ,  Toshio FUJISAWA ,  Keisuke NAKATSUKA ,  Tomoya SANUKI

IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/02

Abstract: According to one embodiment, a storage device includes a stage on which a semiconductor wafer can be mounted, wherein data is capable of being read from the semiconductor wafer or data is capable of being written to the semiconductor wafer. The storage device further includes a plurality of probe pins for reading or writing data, and a controller connected the probe pins. The semiconductor wafer includes electrodes connectable to the probe pins, a first memory area that can store user data, and a second memory area that can store identification information for identification of the semiconductor wafer and a check code for checking integrity of the identification information. The controller is capable of reading the identification information and the check code from the second memory area.