公开(公告)号：US12069855B2

公开(公告)日：2024-08-20

申请号：US17524984

申请日：2021-11-12

Applicant: Kioxia Corporation

Inventor： Yoshiaki Fukuzumi ,  Keisuke Suda ,  Fumiki Aiso ,  Atsushi Fukumoto

IPC: H10B41/27 ,  G11C5/06 ,  G11C16/04 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/06 ,  G11C16/0408 ,  G11C16/0466 ,  H10B43/27

Abstract: A semiconductor memory includes a substrate, a source line layer above the substrate in a memory region and a peripheral region of the substrate, a first insulating layer above the source line layer, a first conductive layer on the first insulating layer in the memory and peripheral regions, an alternating stack of a plurality of second insulating layers and a plurality of second conductive layers on the first conductive layer in the memory region, and a plurality of pillars extending through the alternating stack of the second insulating layers and the second conductive layers, the first conductive layer, and the first insulating layer in the memory region. A bottom end of each of the pillars is in the source line layer in a thickness direction. A carrier density of the source line layer is higher in the memory region than in the peripheral region.

公开(公告)号：US12230326B2

公开(公告)日：2025-02-18

申请号：US17943487

申请日：2022-09-13

Applicant: Kioxia Corporation

Inventor： Keisuke Suda ,  Ryota Suzuki ,  Kenta Yamada

IPC: G11C16/06 ,  G11C5/02 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor memory device includes memory blocks arranged in a first direction and bit lines that are arranged in a second direction, and are arranged with the memory blocks in a third direction. The memory block includes first conductive layers arranged in the third direction, a second conductive layer disposed on a side opposite to the bit lines in the third direction with respect to the first conductive layers, semiconductor layers that extend in the third direction, are opposed to the first conductive layers, have one ends in the third direction electrically connected to the second conductive layer, and have the other ends in the third direction electrically connected to the bit lines, and electric charge accumulating films disposed between the first conductive layers and the semiconductor layers. The first conductive layers and the second conductive layer are separated between the memory blocks.

公开(公告)号：US11637123B2

公开(公告)日：2023-04-25

申请号：US16989168

申请日：2020-08-10

Applicant: Kioxia Corporation

Inventor： Atsushi Fukumoto ,  Keisuke Suda ,  Takayuki Ito

IPC: H01L27/00 ,  H01L27/11582 ,  H01L21/3213 ,  H01L21/311

Abstract: A semiconductor device according to one embodiment is provided with: a substrate; a stacked body provided on the substrate; and a pillar portion penetrating the stacked body. The pillar portion has a first film including a first material and a second material, and a second film provided on an inner side of the first film. The second material is a material that increases an etching rate of the first material as a composition rate relative to the first material is higher, and the composition rate gradually decreases from an upper part to a lower part of the first film.

公开(公告)号：US20210082952A1

公开(公告)日：2021-03-18

申请号：US16989168

申请日：2020-08-10

Applicant: Kioxia Corporation

Inventor： Atsushi Fukumoto ,  Keisuke Suda ,  Takayuki Ito

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/3213

Abstract: A semiconductor device according to one embodiment is provided with: a substrate; a stacked body provided on the substrate; and a pillar portion penetrating the stacked body. The pillar portion has a first film including a first material and a second material, and a second film provided on an inner side of the first film. The second material is a material that increases an etching rate of the first material as a composition rate relative to the first material is higher, and the composition rate gradually decreases from an upper part to a lower part of the first film.