公开(公告)号：US20230324455A1

公开(公告)日：2023-10-12

申请号：US18209398

申请日：2023-06-13

Applicant: Kioxia Corporation

Inventor： Tatsuro HITOMI ,  Yasuhito YOSHIMIZU ,  Masayuki MIURA ,  Arata INOUE ,  Hiroyuki DOHMAE ,  Koichi NAKAZAWA ,  Mitoshi MIYAOKA ,  Kazuhito HAYASAKA ,  Tomoya SANUKI

IPC: G01R31/28 ,  G01R1/073

CPC classification number: G01R31/2886 ,  G01R1/07342

Abstract: According to one embodiment, a wafer includes a substrate including a first region and a second region that do not overlap each other; a first chip unit and a second chip unit each arranged on the substrate; a first electrode and a second electrode each electrically connected to the first chip unit; and a third electrode and a fourth electrode each electrically connected to the second chip unit. The first electrode and the third electrode are arranged in the first region. The second electrode and the fourth electrode are arranged in the second region. The first region is independent of a region in which the first chip unit and the second chip unit are provided.