公开(公告)号：US11935591B2

公开(公告)日：2024-03-19

申请号：US17549337

申请日：2021-12-13

Applicant: Kioxia Corporation

Inventor： Masahiro Takahashi ,  Hiroshi Ito ,  Ryousuke Takizawa

IPC: G11C13/00 ,  G11C5/06

CPC classification number: G11C13/004 ,  G11C5/06 ,  G11C13/0038 ,  G11C13/0069

Abstract: According to one embodiment, a memory device includes a first wiring line, a second wiring line, a memory cell connected between the first and second wiring lines, including a resistance change memory element having first and second resistance states, and a two-terminal switching element connected in series to the resistance change memory element, and a voltage application circuit which applies a write voltage signal having a first polarity and setting a desired resistance state to the resistance change memory element, to the memory cell, and applies, after the write voltage signal is applied to the memory cell, a second polarity voltage signal having a magnitude that prevents the two-terminal switching element from being set to the on-state, to the memory cell.

公开(公告)号：US11651808B2

公开(公告)日：2023-05-16

申请号：US17181035

申请日：2021-02-22

Applicant: Kioxia Corporation

Inventor： Ryousuke Takizawa

IPC: G11C7/12 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693

Abstract: A semiconductor memory device includes a memory cell including a switching element and a resistance change element. A first circuit supplies a constant current to the memory cell for an amount of time and a second circuit applies a constant voltage to the memory cell for an amount of time. The semiconductor memory device places the memory cell into an ON state by applying, while applying a first current to the memory cell by the first circuit, a first voltage to the memory cell by the second circuit and performs readout on the memory cell in the ON state by the first current.

公开(公告)号：US12230322B2

公开(公告)日：2025-02-18

申请号：US17943432

申请日：2022-09-13

Applicant: Kioxia Corporation

Inventor： Ryousuke Takizawa

IPC: G11C11/24 ,  G11C13/00

Abstract: A first switching element in a memory cell is configured to transition from an ON state to an OFF state in response to a voltage applied between its two terminals being decreased. A read circuit is configured to place the second interconnect in a floating state, and, after placing the second interconnect in the floating state and based on a comparison between a first voltage of the second interconnect at a time point of the first switching element becoming the OFF state and a second voltage, either apply a third voltage to the second interconnect and then place the second interconnect in the floating state, or apply a fourth voltage lower than the third voltage to the second interconnect without applying the third voltage to the second interconnect.

公开(公告)号：US11264072B2

公开(公告)日：2022-03-01

申请号：US17021173

申请日：2020-09-15

Applicant: Kioxia Corporation

Inventor： Ryousuke Takizawa

IPC: G11C7/00 ,  G11C11/16

Abstract: According to one embodiment, a memory device includes first and second lines, a memory cell connected between the first and second lines, and including a resistance change memory element and a switching element, a current supply circuit supplying write current to the memory cell when data is written to the resistance change memory element, a detection circuit detecting an on state of the switching element after supply operation of the write current is enabled, and a control circuit controlling a time required until supplying the write current from the current supply circuit is stopped, wherein a starting point of the controlling the time is a time point at which the on state of the switching element is detected.