公开(公告)号：US20220308772A1

公开(公告)日：2022-09-29

申请号：US17465501

申请日：2021-09-02

Applicant: KIOXIA CORPORATION

Inventor： Shinji YONEZAWA ,  Tomoyuki KANTANI

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/26

Abstract: According to one embodiment, a memory system includes first and second memory chips. The first memory chip has a first plane with a first block and a second block and a second plane with a third block and a fourth block. The second memory chip has a third plane with a fifth block and a sixth block and a fourth plane with a seventh block and an eighth block. The memory controller sets the first and third blocks as a first block unit in a user data storage area and the fifth and seventh blocks as a second block unit in the user data storage area. The memory controller allocates the second block, the fourth block, the sixth block, and the eighth block to a management data storage area. The memory controller manages user data operations for accessing the user data storage area in block units.

公开(公告)号：US20240302997A1

公开(公告)日：2024-09-12

申请号：US18594070

申请日：2024-03-04

Applicant: Kioxia Corporation

Inventor： Konosuke WATANABE ,  Shinji YONEZAWA ,  Eiji SUKIGARA ,  Mitsusato HARA ,  Haruka MORI ,  Hajime YAMAZAKI

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0688

Abstract: According to one embodiment, a memory system includes a plurality of nonvolatile memory chips and a controller. The controller manages whether each of the nonvolatile memory chips is in a busy state or not. When one or more requests issued by a host are stored in at least one queue of the host, the controller identifies, from the one or more requests, a first request for a first nonvolatile memory chip that is not in the busy state. The controller executes a process in accordance with the identified first request.

公开(公告)号：US20220093155A1

公开(公告)日：2022-03-24

申请号：US17201127

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Shinji YONEZAWA

IPC: G11C11/4074 ,  G11C11/4072 ,  G11C11/4093 ,  G11C5/14

Abstract: According to on embodiment, a memory system includes a non-volatile memory, a memory controller including a data buffer configured to store first data, and a backup power supply configured to supply first power to the non-volatile memory and the memory controller, when second power from an external main power supply is off. The memory controller is configured to write second data including information identifying the first data in the non-volatile memory without writing the first data in the non-volatile memory, when the first power is supplied from the backup power supply, and transmit the information stored in the non-volatile memory to an external host device, after a recovery of the second power from the main power supply.