公开(公告)号：US20210091221A1

公开(公告)日：2021-03-25

申请号：US16816871

申请日：2020-03-12

Applicant: Kioxia Corporation

Inventor： Tadayoshi UECHI ,  Takashi IZUMIDA

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238

Abstract: According to one embodiment, a semiconductor device includes an element region, an element isolation region adjacent to the element region, a gate insulating layer provided on an upper surface of the element region, and a gate electrode including a semiconductor layer, the semiconductor layer containing boron (B) and including a portion provided on the gate insulating layer, the element isolation region including an upper portion including an upper surface of the element isolation region and a lower portion including a lower surface of the element isolation region, and the upper portion of the element isolation region applying compressive stress to a portion of the element region, which is adjacent to the upper portion of the element isolation region.

公开(公告)号：US20220216228A1

公开(公告)日：2022-07-07

申请号：US17656143

申请日：2022-03-23

Applicant: Kioxia Corporation

Inventor： Tetsuya YAMASHITA ,  Takuyo NAKAYAMA ,  Takashi ICHIKAWA ,  Tadayoshi UECHI ,  Takashi IZUMIDA

IPC: H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

Abstract: According to one embodiment, a semiconductor memory device includes a first stacked body in which a plurality of first conductive layers are stacked at intervals in a first direction above a semiconductor substrate; a second stacked body in which a plurality of second conductive layers are stacked at intervals in the first direction above the semiconductor substrate; and a first slit extending in a second direction perpendicular to the first direction, the first slit isolating the first stacked body and the second stacked body in a third direction perpendicular to the first and second directions.

公开(公告)号：US20220084984A1

公开(公告)日：2022-03-17

申请号：US17188308

申请日：2021-03-01

Applicant: Kioxia Corporation

Inventor： Michihito KONO ,  Takashi IZUMIDA ,  Tadayoshi UECHI ,  Takeshi SHIMANE

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor memory device, includes: a first region including a memory cell array; and a second region including a peripheral circuit. The second region includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes: a semiconductor region between the first and second surfaces; an n-type semiconductor region provided on the first surface and higher in donor concentration than the semiconductor region; a damaged region provided on the second surface; and a p-type semiconductor region provided between the damaged region and the n-type semiconductor region, closer to the second surface than the n-type semiconductor region in a direction from the first surface toward the second surfaces of the semiconductor substrate, and higher in acceptor concentration than the semiconductor region.

公开(公告)号：US20210091044A1

公开(公告)日：2021-03-25

申请号：US16801312

申请日：2020-02-26

Applicant: Kioxia Corporation

Inventor： Tetsuya YAMASHITA ,  Takuyo NAKAYAMA ,  Takashi ICHIKAWA ,  Tadayoshi UECHI ,  Takashi IZUMIDA

IPC: H01L25/065 ,  H01L27/11578 ,  H01L27/11575

Abstract: According to one embodiment, a semiconductor memory device includes a first stacked body in which a plurality of first conductive layers are stacked at intervals in a first direction above a semiconductor substrate; a second stacked body in which a plurality of second conductive layers are stacked at intervals in the first direction above the semiconductor substrate; and a first slit extending in a second direction perpendicular to the first direction, the first slit isolating the first stacked body and the second stacked body in a third direction perpendicular to the first and second directions.