公开(公告)号：US20220216228A1

公开(公告)日：2022-07-07

申请号：US17656143

申请日：2022-03-23

Applicant: Kioxia Corporation

Inventor： Tetsuya YAMASHITA ,  Takuyo NAKAYAMA ,  Takashi ICHIKAWA ,  Tadayoshi UECHI ,  Takashi IZUMIDA

IPC: H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

Abstract: According to one embodiment, a semiconductor memory device includes a first stacked body in which a plurality of first conductive layers are stacked at intervals in a first direction above a semiconductor substrate; a second stacked body in which a plurality of second conductive layers are stacked at intervals in the first direction above the semiconductor substrate; and a first slit extending in a second direction perpendicular to the first direction, the first slit isolating the first stacked body and the second stacked body in a third direction perpendicular to the first and second directions.

公开(公告)号：US20210091044A1

公开(公告)日：2021-03-25

申请号：US16801312

申请日：2020-02-26

Applicant: Kioxia Corporation

Inventor： Tetsuya YAMASHITA ,  Takuyo NAKAYAMA ,  Takashi ICHIKAWA ,  Tadayoshi UECHI ,  Takashi IZUMIDA

IPC: H01L25/065 ,  H01L27/11578 ,  H01L27/11575

Abstract: According to one embodiment, a semiconductor memory device includes a first stacked body in which a plurality of first conductive layers are stacked at intervals in a first direction above a semiconductor substrate; a second stacked body in which a plurality of second conductive layers are stacked at intervals in the first direction above the semiconductor substrate; and a first slit extending in a second direction perpendicular to the first direction, the first slit isolating the first stacked body and the second stacked body in a third direction perpendicular to the first and second directions.

公开(公告)号：US20230086773A1

公开(公告)日：2023-03-23

申请号：US17693617

申请日：2022-03-14

Applicant: Kioxia Corporation

Inventor： Akira YOTSUMOTO ,  Keisuke SUDA ,  Kenji TASHIRO ,  Tetsuya YAMASHITA ,  Daigo ICHINOSE

IPC: H01L27/11565 ,  H01L27/11582

Abstract: According to one embodiment, a semiconductor memory device includes: a stacked body having a stacked structure in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one, the stacked body including a memory region and a dummy region arranged in a first direction intersecting a stacking direction of the plurality of conductive layers, the dummy region including a first stepped portion in which at least a part of the plurality of conductive layers on an upper layer side is processed in a stepped shape and terminates at an end portion opposite to the memory region in the first direction; and first and second plate-like portions extending in the stacking direction and the first direction in the stacked body at positions in the memory region away from each other in a second direction intersecting the stacking direction and the first direction, the first and second plate-like portions being directly or indirectly connected to each other and terminating in the dummy region, each of the first and second plate-like portions dividing the stacked body excluding at least a part of the end portion of the dummy region in the second direction.