公开(公告)号：US20240098983A1

公开(公告)日：2024-03-21

申请号：US18359531

申请日：2023-07-26

Applicant: Kioxia Corporation

Inventor： Takashi Inukai

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/33 ,  H10B12/485 ,  H10B12/50

Abstract: According to one embodiment, a memory device includes word lines, bit lines, transistors, capacitors, and a plate line. The transistors include first transistors and second transistors. The first and second transistors are coupled to first and second word lines, respectively. The first and second transistors are arranged to alternate each other in a first direction. The bit lines include first to fourth bit lines arranged sequentially in the first direction. The first and third bit lines are coupled to the other end of the first and second transistors. The second bit line is coupled to the other end of the first transistors and is not coupled to the other end of the second transistors. The fourth bit line is coupled to the other end of the second transistors and is not coupled to the other end of the first transistors.

公开(公告)号：US20240098977A1

公开(公告)日：2024-03-21

申请号：US18467887

申请日：2023-09-15

Applicant: Kioxia Corporation

Inventor： Takashi Inukai ,  Hiroki Tokuhira ,  Tsuneo Inaba

IPC: H10B12/00

CPC classification number: H10B12/33 ,  H10B12/482 ,  H10B12/488

Abstract: According to one embodiment, a semiconductor device includes a first wiring line provided in a first layer and extending in a first direction, a second wiring line provided in a second layer and extending in the first direction, a first semiconductor layer penetrating the first wiring line without penetrating the second wiring line and extending in a second direction, a second semiconductor layer penetrating the second wiring line without penetrating the first wiring line and extending in the second direction, a first insulating layer provided between the first wiring line and the first semiconductor layer, a second insulating layer provided between the second wiring line and the second semiconductor layer.