公开(公告)号：US20210090645A1

公开(公告)日：2021-03-25

申请号：US16910826

申请日：2020-06-24

申请人： Kioxia Corporation

发明人： Tsuneo Inaba ,  Atsushi Kawasumi

IPC分类号： G11C13/00 ,  G11C11/16

摘要： According to an embodiment, a memory device includes a first memory cell and a second memory cell each including a variable resistance element and a switching element, and includes a read and write circuit. The circuit is configured to perform, as a first access, a write operation or a read operation on the first memory cell, and make a second access after the first access. As the second access, data is written into or read from the second memory cell, under a condition based on a type of the first access.

公开(公告)号：US20220285350A1

公开(公告)日：2022-09-08

申请号：US17824780

申请日：2022-05-25

申请人： Kioxia Corporation

发明人： Mutsumi Okajima ,  Tsuneo Inaba ,  Hiromitsu Mashita

IPC分类号： H01L27/108 ,  H01L29/786 ,  H01L29/66

摘要： According to one embodiment, a memory includes: a first transistor including: a first semiconductor between the substrate and the bit line; and a first gate facing a side of the first semiconductor; a first memory element between the first transistor and the substrate; a first word line including a first conductor coupled to the first gate; a second transistor including: a second semiconductor between the substrate and the bit line; and a second gate facing a side of the second semiconductor; a second memory element between the second transistor and the substrate; and a second word line being adjacent to the first word line in a first direction and including a second conductor coupled to the second gate. The second semiconductor is adjacent to the first semiconductor in a second direction intersecting the first direction.

公开(公告)号：US11100988B2

公开(公告)日：2021-08-24

申请号：US17016185

申请日：2020-09-09

申请人： Kioxia Corporation

发明人： Tsuneo Inaba ,  Hiroyuki Takenaka ,  Akihiko Chiba

IPC分类号： G11C13/00 ,  H01L27/24

摘要： According to one embodiment, a semiconductor memory device includes the following configuration. First Lower word line drivers are arranged between adjacent mats, and first upper word line drivers are arranged between the first Lower word line drivers. Second Lower word line drivers are arranged between another adjacent mats, and second upper word line drivers are arranged between the second lower word line drivers. The first and second upper word line drivers are shared by the adjacent mats respectively.

公开(公告)号：US11665882B2

公开(公告)日：2023-05-30

申请号：US17012676

申请日：2020-09-04

申请人： Kioxia Corporation

发明人： Masaharu Wada ,  Mutsumi Okajima ,  Tsuneo Inaba ,  Shinji Miyano

IPC分类号： H01L27/10 ,  H01L27/108 ,  G11C11/407

CPC分类号： H01L27/10808 ,  H01L27/1082 ,  H01L27/10832 ,  H01L27/10897 ,  G11C11/407

摘要： A semiconductor memory device, includes: a first region including a first memory cell array; a second region arranged with the first region; and a third region arranged with the second region and including a second memory cell array. Each memory cell array includes: a field effect transistor above a semiconductor substrate, including a gate, a source, and a drain, the gate being connected to a first wiring, and one of the source and the drain being connected to a second wiring; and a capacitor below the transistor, including a first electrode connected to the other of the source and the drain, a second electrode facing the first electrode, and a third electrode connected to the second electrode and extending to the second region. The second region includes a conductor, the conductor connecting the third electrodes of the memory cell arrays.

公开(公告)号：US11094698B2

公开(公告)日：2021-08-17

申请号：US17019642

申请日：2020-09-14

申请人： Kioxia Corporation

发明人： Tsuneo Inaba

IPC分类号： G11C11/24 ,  H01L27/108 ,  G11C11/4097 ,  G11C11/4091

摘要： A semiconductor storage device according to the present embodiment includes a plurality of first wires provided above a surface of a semiconductor substrate to extend in a first direction, and a plurality of second wires provided above the first wires to extend in a second direction crossing the first direction. A plurality of capacitor elements are arranged every other intersection region among intersection regions between the first wires and the second wires as viewed from above the surface of the semiconductor substrate. A plurality of transistors are provided above the capacitor elements to correspond thereto, respectively. A first distance between two of the capacitor elements, which are adjacent to each other in the first direction, is narrower than a second distance between two of the capacitor elements, which are adjacent to each other in the second direction.

公开(公告)号：US11062770B2

公开(公告)日：2021-07-13

申请号：US16910826

申请日：2020-06-24

申请人： KIOXIA CORPORATION

发明人： Tsuneo Inaba ,  Atsushi Kawasumi

IPC分类号： G11C11/00 ,  G11C13/00 ,  G11C11/16

摘要： According to an embodiment, a memory device includes a first memory cell and a second memory cell each including a variable resistance element and a switching element, and includes a read and write circuit. The circuit is configured to perform, as a first access, a write operation or a read operation on the first memory cell, and make a second access after the first access. As the second access, data is written into or read from the second memory cell, under a condition based on a type of the first access.

公开(公告)号：US20240098977A1

公开(公告)日：2024-03-21

申请号：US18467887

申请日：2023-09-15

申请人： Kioxia Corporation

发明人： Takashi Inukai ,  Hiroki Tokuhira ,  Tsuneo Inaba

IPC分类号： H10B12/00

CPC分类号： H10B12/33 ,  H10B12/482 ,  H10B12/488

摘要： According to one embodiment, a semiconductor device includes a first wiring line provided in a first layer and extending in a first direction, a second wiring line provided in a second layer and extending in the first direction, a first semiconductor layer penetrating the first wiring line without penetrating the second wiring line and extending in a second direction, a second semiconductor layer penetrating the second wiring line without penetrating the first wiring line and extending in the second direction, a first insulating layer provided between the first wiring line and the first semiconductor layer, a second insulating layer provided between the second wiring line and the second semiconductor layer.