公开(公告)号：US20210074355A1

公开(公告)日：2021-03-11

申请号：US16807850

申请日：2020-03-03

Applicant: KIOXIA CORPORATION

Inventor： Takayuki TSUKAMOTO ,  Hironobu FURUHASHI ,  Takeshi SUGIMOTO ,  Masanori KOMURA

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: A semiconductor memory device includes: first wirings; second wirings intersecting the first wirings; and memory cells. Each of the memory cells is respectively formed between one of the first wirings and one of the second wirings. In a set operation, a set pulse is supplied between one of the first wirings and one of the second wirings. In a reset operation, a reset pulse is supplied between one of the first wirings and one of the second wirings. In a first operation, a first pulse is supplied between one of the first wirings and one of the second wirings. the first pulse has an amplitude equal to or greater than the greater of an amplitude of the set pulse and an amplitude of the reset pulse and has a pulse width greater than a pulse width of the set pulse.

公开(公告)号：US20240321323A1

公开(公告)日：2024-09-26

申请号：US18589351

申请日：2024-02-27

Applicant: Kioxia Corporation

Inventor： Takeshi SUGIMOTO

IPC: G11C5/10 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C5/10 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4096

Abstract: A memory device includes memory cells for each of layers arranged in a first direction, the memory cells of each layer including groups of memory cells, the memory cells of each group being arranged in a second direction intersecting the first direction, the groups being arranged in a third direction intersecting the first and second directions, first wirings arranged in the third direction in each layer and respectively connected to the groups in each layer, first transistors each connected to a corresponding first wiring, second wirings each connected to the first transistors of a corresponding layer, third wirings each extending in the first direction and connected to a memory cell in each layer, and fourth wirings each extending in the first direction and connected to a gate of a corresponding first transistor in each layer.

公开(公告)号：US20230410886A1

公开(公告)日：2023-12-21

申请号：US18081265

申请日：2022-12-14

Applicant: Kioxia Corporation

Inventor： Takeshi SUGIMOTO ,  Takayuki MIYAZAKI

IPC: G11C11/4091 ,  G11C11/4096 ,  G11C11/4099

CPC classification number: G11C11/4091 ,  G11C11/4099 ,  G11C11/4096

Abstract: A memory includes first cell layers respectively including first cells, and a second cell layer including dummy cells. A first wire is connected to the first cells arrayed in a first direction. A second wire is connected to the dummy cells arrayed in the first direction. A third wire is connected to the first cells and one of the dummy cells arrayed in a second direction. A fourth wire is connected to the third wires arrayed in a third direction. A first voltage is applied to a selected first wire when reading data from a selected first cell, and transmits a read data to a selected fourth wire connected to the selected first cell. A reference voltage is applied to a non-selected fourth wire. A second voltage is applied to a selected second wire provided with the dummy cell between the selected second wire and the non-selected fourth wire.

公开(公告)号：US20220076743A1

公开(公告)日：2022-03-10

申请号：US17348005

申请日：2021-06-15

Applicant: Kioxia Corporation

Inventor： Takeshi SUGIMOTO ,  Atsushi KAWASUMI

IPC: G11C13/00

Abstract: According to the embodiment, in a first period, the semiconductor storage device maintains the switch in an ON state. In a second period, the semiconductor storage device performs a first operation, a second operation and a third operation while maintaining the switch in an OFF state. The second period is a period after the first period. The first operation is an operation to supply the first pulse having the first polarity from the first pulse generation circuit to the other end of the first capacitive element. The second operation is an operation to supply the second pulse having the second polarity from the second pulse generation circuit to the other end of the second capacitive element. The third operation is an operation to connect the first bit line to the first data line.