公开(公告)号：US11778808B2

公开(公告)日：2023-10-03

申请号：US17472902

申请日：2021-09-13

申请人： Kioxia Corporation

发明人： Teruhisa Sonohara ,  Shunichi Seno ,  Hiroki Tokuhira ,  Fumitaka Arai

IPC分类号： G11C11/24 ,  H10B12/00 ,  H01L29/786 ,  G11C11/4076 ,  H01L29/66 ,  G11C11/406 ,  G11C11/4096 ,  H01L21/02

CPC分类号： H10B12/30 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/40615 ,  H01L21/02565 ,  H01L29/66969 ,  H01L29/7869 ,  H10B12/03 ,  H10B12/05

摘要： A semiconductor memory device includes: a first wiring; a first semiconductor layer connected to the first wiring, the first semiconductor layer; a first electrode, the first electrode being connected to the first semiconductor layer; a second electrode disposed between the first electrode and the first wiring, the second electrode being opposed to the first semiconductor layer; a third electrode disposed between the second electrode and the first wiring, the third electrode; a second semiconductor layer disposed between the third electrode and the first semiconductor layer, the second semiconductor layer being opposed to the third electrode; and an electric charge accumulating layer electrically connected to the first wiring via the second semiconductor layer, the electric charge accumulating layer being opposed to the first semiconductor layer.

公开(公告)号：US12127391B2

公开(公告)日：2024-10-22

申请号：US18458054

申请日：2023-08-29

申请人： Kioxia Corporation

发明人： Teruhisa Sonohara ,  Shunichi Seno ,  Hiroki Tokuhira ,  Fumitaka Arai

IPC分类号： G11C11/24 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786 ,  H10B12/00

CPC分类号： H10B12/30 ,  G11C11/40615 ,  G11C11/4076 ,  G11C11/4096 ,  H01L21/02565 ,  H01L29/66969 ,  H01L29/7869 ,  H10B12/03 ,  H10B12/05

摘要： A semiconductor memory device includes: a first wiring; a first semiconductor layer connected to the first wiring, the first semiconductor layer; a first electrode, the first electrode being connected to the first semiconductor layer; a second electrode disposed between the first electrode and the first wiring, the second electrode being opposed to the first semiconductor layer; a third electrode disposed between the second electrode and the first wiring, the third electrode; a second semiconductor layer disposed between the third electrode and the first semiconductor layer, the second semiconductor layer being opposed to the third electrode; and an electric charge accumulating layer electrically connected to the first wiring via the second semiconductor layer, the electric charge accumulating layer being opposed to the first semiconductor layer.