公开(公告)号：US20230420067A1

公开(公告)日：2023-12-28

申请号：US18053896

申请日：2022-11-09

Applicant: Kioxia Corporation

Inventor： Marie TAKADA ,  Masanobu SHIRAKAWA ,  Hideki YAMADA ,  Ryo YAMAKI

IPC: G11C29/52 ,  G11C11/4096 ,  G11C11/4074

CPC classification number: G11C29/52 ,  G11C11/4096 ,  G11C11/4074

Abstract: A memory system includes a nonvolatile memory including memory cells each configured to store first and second bits, and a memory controller. The memory controller is configured to: read first data by using a first voltage to a first read process that reads data corresponding to the first bit from the memory cells; read second data by using a second voltage to a second read process that reads data corresponding to the second bit from the memory cells; in a case where an error correction process of the first data is successful, determine a third voltage, based on the first data and third data that is obtained by error-correcting the first data; and update a first read voltage that is used to the first read process, from the first voltage to the third voltage.

公开(公告)号：US20230213348A1

公开(公告)日：2023-07-06

申请号：US18178905

申请日：2023-03-06

Applicant: KIOXIA CORPORATION

Inventor： Hideki YAMADA ,  Masanobu SHIRAKAWA ,  Marie KURONAGA

IPC: G01C21/36 ,  H04W4/40 ,  G01C21/34 ,  G05D1/00 ,  G06V20/59 ,  G06V10/75

CPC classification number: G01C21/36 ,  H04W4/40 ,  G01C21/3438 ,  G01C21/3605 ,  G05D1/0088 ,  G06V20/59 ,  G06V10/75 ,  G05D2201/0213

Abstract: According to one embodiment, an information processing device includes: a first memory; a first receiver; a first determination section; and a first transmitter. The first memory is configured to store first image data of interior of a vehicle at a first point in time. The first receiver is configured to receive second image data of the interior of the vehicle at a second point of time from the vehicle. The first determination section is configured to determine whether a change has been caused in the interior of the vehicle between the first point in time and the second point in time. The first transmitter is configured to transmit first data based on the determination result.

公开(公告)号：US20220068402A1

公开(公告)日：2022-03-03

申请号：US17190638

申请日：2021-03-03

Applicant: Kioxia Corporation

Inventor： Hideki YAMADA ,  Masanobu SHIRAKAWA

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08

Abstract: According to the one embodiment, a memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes: first and second memory cells stacked above a substrate; a first word line coupled to the first and second memory cells; a first bit line coupled to the first memory cell; and a second bit line coupled to the second memory cell. A first state read operation includes a first read operation for reading data from the first memory cell and a second read operation for reading data from the second memory cell. A first read voltage is applied to the first word line during a first period for executing the first read operation, and a second read voltage is applied to the first word line during a second period for executing the second read operation.

公开(公告)号：US20220414553A1

公开(公告)日：2022-12-29

申请号：US17903333

申请日：2022-09-06

Applicant: Kioxia Corporation

Inventor： Hideki YAMADA ,  Masanobu SHIRAKAWA ,  Marie KURONAGA ,  Hideki KAWASAKI

IPC: G06Q10/02

Abstract: An information processing device to reserve a parking lot for a vehicle includes a reception unit; a first retrieval unit; a second retrieval unit; and a reservation unit. The reception unit receives first information regarding a destination of the vehicle. The first retrieval unit retrieves a route to the destination based on the first information. The second retrieval unit retrieves a route to the destination, a first area around the route, and first time. The reservation unit requests a reservation for a first parking lot in the first area at the first time using wireless or wired communication without waiting for an instruction from a user.

公开(公告)号：US20250022498A1

公开(公告)日：2025-01-16

申请号：US18764581

申请日：2024-07-05

Applicant: Kioxia Corporation

Inventor： Shogo MUTO ,  Masanobu SHIRAKAWA ,  Hideki YAMADA ,  Ryo YAMAKI ,  Yoshihiro UEDA ,  Tsuyoshi KONDO

IPC: G11C11/16 ,  G11C19/08 ,  H10B61/00 ,  H10N50/10

Abstract: A first circuit outputs first information indicating presence/absence of a magnetic wall between two adjacent portions among portions of a magnetic body, and second information based on the combination of magnetization states of the two portions. A first storage circuit stores first bits corresponding to the portions. A most significant bit of the first bits has a value independent of a magnetization state of a corresponding one of the portions, and the first bits have a value based on the first information. A second storage circuit stores the second information. The second circuit causes the first storage circuit to output the first bits when a value of a least significant bit of the first bits matches a value of the second information, and otherwise third bits having inverse values of the first bits.

公开(公告)号：US20230047861A1

公开(公告)日：2023-02-16

申请号：US17976566

申请日：2022-10-28

Applicant: Kioxia Corporation

Inventor： Kengo KUROSE ,  Masanobu SHIRAKAWA ,  Hideki YAMADA ,  Marie TAKADA

IPC: G11C16/16 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G06F3/06

Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell configured to store data. The controller is configured to output a first parameter and a first command. The first parameter relates to an erase voltage for a first erase operation with respect to the first memory cell. The first command instructs the first erase operation. The controller outputs the first command after outputting the first parameter to the semiconductor memory device.

公开(公告)号：US20220066688A1

公开(公告)日：2022-03-03

申请号：US17201092

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Kengo KUROSE ,  Masanobu SHIRAKAWA ,  Naomi TAKEDA ,  Hideki YAMADA

IPC: G06F3/06

Abstract: According to one embodiment, a shift register memory writes data having a first size corresponding to a capacity of a block to a plurality of layers of a plurality of data storing shift strings included in the block, in response to a first command sequence specifying a first write mode from a controller. In response to a second command sequence specifying a second write mode from the controller, the shift register memory writes data having a second size smaller than the capacity of the block to the plurality of layers of one or more first data storing shift strings of the plurality of data storing shift strings, without writing data to each of other data storing shift strings except the one or more first data storing shift strings.

公开(公告)号：US20210082510A1

公开(公告)日：2021-03-18

申请号：US16802428

申请日：2020-02-26

Applicant: KIOXIA CORPORATION

Inventor： Hideki YAMADA ,  Marie TAKADA ,  Masanobu SHIRAKAWA

IPC: G11C16/10 ,  G11C16/04 ,  G06F3/06

Abstract: In connection with a write operation, a memory controller transmits a first command sequence to a memory chip, thereby causing the memory chip to execute a first-stage program operation that includes a first operation and a first part of a second operation after the first operation, and a second command sequence to the memory chip after the first-stage program operation is executed, thereby causing the memory chip to execute a second-stage program operation that includes a second part of the second operation and no part of the first operation. During the first operation, a program voltage is applied a plurality of times while increasing the program voltage each of the times by a first step size. During the second operation, the program voltage is applied a plurality of times while increasing the program voltage each of the times by a second step size smaller than the first step size.

公开(公告)号：US20230090202A1

公开(公告)日：2023-03-23

申请号：US17686148

申请日：2022-03-03

Applicant: KIOXIA CORPORATION

Inventor： Takumi FUJIMORI ,  Tetsuya SUNATA ,  Masanobu SHIRAKAWA ,  Hideki YAMADA

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34

Abstract: A memory device includes a first block including a first memory cell and a first word line connected to the first memory cell, a second block including a second memory cell and a second word line connected to the second memory cell, and a control circuit. The control circuit applies a first voltage to each of the first and second word lines to supply a first erase pulse having a first erase intensity to each of the first and second blocks, when a first erase operation is executed, and applies the first voltage to the first word line and a second voltage higher than the first voltage to the second word line, to supply the first erase pulse to the first block and a second erase pulse having a second erase intensity less than the first erase intensity to the second block, when a second erase operation is executed.

公开(公告)号：US20220093199A1

公开(公告)日：2022-03-24

申请号：US17202432

申请日：2021-03-16

Applicant: Kioxia Corporation

Inventor： Masanobu SHIRAKAWA ,  Hideki YAMADA ,  Marie TAKADA

IPC: G11C29/42 ,  G11C29/20 ,  G11C29/12

Abstract: A memory system according to an embodiment includes a memory device, and a memory controller. The memory device includes first and second memory cells, a first word line, and first and second bit lines. The first and second memory cells are provided in first and second layers, respectively. The first word line is coupled to the first memory cell and the second memory cell. The first bit line is coupled to the first memory cell. The second bit line is coupled to the second memory cell. The memory controller includes a storage circuit capable of storing a correction value table. The correction value table is configured to store a first correction value of a read voltage associated with the first layer and a second correction voltage of a read voltage associated with the second layer.