公开(公告)号：US20210257336A1

公开(公告)日：2021-08-19

申请号：US17007849

申请日：2020-08-31

Applicant: Kioxia Corporation

Inventor： Takeori MAEDA ,  Yuusuke TAKANO ,  Soichi HOMMA

IPC: H01L25/065 ,  H01L21/306 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/00

Abstract: A semiconductor device includes a first semiconductor chip having a first surface and a second surface; a first adhesive layer on the first surface; a second semiconductor chip that includes a third surface and a fourth surface, and a connection bump on the third surface. The connection bump is coupled to the first adhesive layer. The semiconductor device includes a wiring substrate connected to the connection bump. The semiconductor device includes a first resin layer covering the connection bump between the second semiconductor chip and the wiring substrate, and covers one side surface of the second semiconductor chip connecting the third surface and the fourth surface. The first adhesive layer covers an upper portion of the at least one side surface. The first resin layer covers a lower portion of the at least one side surface. The first adhesive layer and the first resin layer contact each other.

公开(公告)号：US20220216184A1

公开(公告)日：2022-07-07

申请号：US17701328

申请日：2022-03-22

Applicant: Kioxia Corporation

Inventor： Takeori MAEDA ,  Yuusuke TAKANO ,  Soichi HOMMA

IPC: H01L25/065 ,  H01L21/306 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/00

Abstract: A semiconductor device includes a first semiconductor chip having a first surface and a second surface; a first adhesive layer on the first surface; a second semiconductor chip that includes a third surface and a fourth surface, and a connection bump on the third surface. The connection bump is coupled to the first adhesive layer. The semiconductor device includes a wiring substrate connected to the connection bump. The semiconductor device includes a first resin layer covering the connection bump between the second semiconductor chip and the wiring substrate, and covers one side surface of the second semiconductor chip connecting the third surface and the fourth surface. The first adhesive layer covers an upper portion of the at least one side surface. The first resin layer covers a lower portion of the t least one side surface. The first adhesive layer and the first resin layer contact each other.

公开(公告)号：US20240321830A1

公开(公告)日：2024-09-26

申请号：US18596484

申请日：2024-03-05

Applicant: Kioxia Corporation

Inventor： Hayato FURUICHI ,  Yuusuke TAKANO ,  Tatsuo MIGITA

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/544

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/544 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2223/54426 ,  H01L2224/16145 ,  H01L2224/81 ,  H01L2224/94 ,  H01L2225/06541

Abstract: A manufacturing method of a semiconductor device, includes mounting on a first substrate a plurality of second substrates at a predetermined interval, the first substrate including a wiring layer, each of the second substrates including a plurality of semiconductor cells separated from each other by a boundary portion, forming a first recess on the first substrate between two of the second substrates that are adjacent to each other, cutting each of the second substrates along the boundary portion thereof to form a gap and a second recess on the first substrate through the gap, forming a sealing member on the first substrate, and cutting the first substrate together with the sealing member along lines extending along and inside the first and second recesses to individualize the semiconductor cells.

公开(公告)号：US20240203901A1

公开(公告)日：2024-06-20

申请号：US18539487

申请日：2023-12-14

Applicant: Kioxia Corporation

Inventor： Toshihiko OHDA ,  Yuusuke TAKANO

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06562

Abstract: A semiconductor device includes a wiring board having a first surface and a ground electrode exposed to the first surface, a stacked body provided above the first surface and having a chip structure body and a first resin layer that seals the chip structure body, a second resin layer that seals the stacked body, a third resin layer provided between the wiring board and the stacked body, and a first conductive shield layer provided between the first resin layer and the first surface and between the first resin layer and the second resin layer, and being in contact with the ground electrode. The first conductive shield layer is in contact with the side surface of the first resin layer. When looking the ground electrode from a direction perpendicular to the first surface, the ground electrode is provided outside of the first resin layer.