公开(公告)号：US08023565B2

公开(公告)日：2011-09-20

申请号：US11475172

申请日：2006-06-27

申请人： Tatsuhiro Suzumura ,  Akihiro Oue ,  Kunihiko Yahagi ,  Shuji Michinaka ,  Satoshi Takekawa ,  Kiwamu Watanabe

发明人： Tatsuhiro Suzumura ,  Akihiro Oue ,  Kunihiko Yahagi ,  Shuji Michinaka ,  Satoshi Takekawa ,  Kiwamu Watanabe

IPC分类号： H04N7/18

CPC分类号： H04N19/423 ,  H04N19/44 ,  H04N19/61

摘要： A picture processing apparatus includes a decoder configured to decode encoded data to generate a decoded picture. A picture memory has a plurality of banks each containing a plurality of pages to which row addresses are assigned, and is configured to store the decoded picture. A bank selector is configured to divide the decoded picture into a plurality of blocks, and to select a page of a different bank as a write location for a block adjacent in at least one of either a horizontal direction or a vertical direction. A write controller is configured to write pixel data of pixels occupying even lines of each of the blocks, and pixel data of pixels occupying odd lines of each of the blocks in a column address direction of each of the page in an alternating manner.

摘要翻译： 图像处理装置包括：解码器，被配置为对编码数据进行解码以生成解码图像。 图像存储器具有多个存储体，每个存储体包含分配了行地址的多个页面，并且被配置为存储解码图像。 存储体选择器被配置为将解码图像划分为多个块，并且选择不同存储体的页作为在水平方向或垂直方向中的至少一个中相邻的块的写入位置。 写入控制器被配置为写入占据每个块的偶数行的像素的像素数据，并且以交替的方式在每个页面的列地址方向上占据每个块的奇数行的像素的像素数据。

公开(公告)号：US20060291568A1

公开(公告)日：2006-12-28

申请号：US11475172

申请日：2006-06-27

申请人： Tatsuhiro Suzumura ,  Akihiro Oue ,  Kunihiko Yahagi ,  Shuji Michinaka ,  Satoshi Takekawa ,  Kiwamu Watanabe

发明人： Tatsuhiro Suzumura ,  Akihiro Oue ,  Kunihiko Yahagi ,  Shuji Michinaka ,  Satoshi Takekawa ,  Kiwamu Watanabe

IPC分类号： H04N11/04

CPC分类号： H04N19/423 ,  H04N19/44 ,  H04N19/61

摘要： A picture processing apparatus includes a decoder configured to decode encoded data to generate a decoded picture. A picture memory has a plurality of banks each containing a plurality of pages to which row addresses are assigned, and is configured to store the decoded picture. A bank selector is configured to divide the decoded picture into a plurality of blocks, and to select a page of a different bank as a write location for a block adjacent in at least one of either a horizontal direction or a vertical direction. A write controller is configured to write pixel data of pixels occupying even lines of each of the blocks, and pixel data of pixels occupying odd lines of each of the blocks in a column address direction of each of the page in an alternating manner.

摘要翻译： 图像处理装置包括：解码器，被配置为对编码数据进行解码以生成解码图像。 图像存储器具有多个存储体，每个存储体包含分配了行地址的多个页面，并且被配置为存储解码图像。 存储体选择器被配置为将解码图像划分为多个块，并且选择不同存储体的页作为在水平方向或垂直方向中的至少一个中相邻的块的写入位置。 写入控制器被配置为写入占据每个块的偶数行的像素的像素数据，并且以交替的方式在每个页面的列地址方向上占据每个块的奇数行的像素的像素数据。

公开(公告)号：US08155204B2

公开(公告)日：2012-04-10

申请号：US11857874

申请日：2007-09-19

申请人： Tatsuhiro Suzumura ,  Shuji Michinaka ,  Kiwamu Watanabe ,  Masashi Jobashi ,  Takaya Ogawa ,  Hiromitsu Nakayama ,  Satoshi Takekawa ,  Yoshinori Shigeta ,  Akihiro Oue

发明人： Tatsuhiro Suzumura ,  Shuji Michinaka ,  Kiwamu Watanabe ,  Masashi Jobashi ,  Takaya Ogawa ,  Hiromitsu Nakayama ,  Satoshi Takekawa ,  Yoshinori Shigeta ,  Akihiro Oue

IPC分类号： H04N11/02

CPC分类号： H04N19/423 ,  H04N19/105 ,  H04N19/112 ,  H04N19/44 ,  H04N19/61

摘要： The image decoding apparatus and the image decoding method according to one aspect of the present invention have a configuration for storing an image decoded in the past as a reference picture into a frame memory, in a field structure in which top lines in the reference picture are stored in a top area and bottom lines in the reference picture are stored in a bottom area, in order to use a part of the image decoded in the past as a reference block in a picture being presently decoded; and selectively copying and storing an uppermost top line or an uppermost bottom line in the reference picture to areas on the uppermost top line and the uppermost bottom line in the reference picture in the top area and the bottom area in the frame memory, and selectively copying and storing a lowermost top line or a lowermost bottom line in the reference picture to areas under the lowermost top line and the lowermost bottom line in the reference picture in the top area and the bottom area in the frame memory.

摘要翻译： 根据本发明的一个方面的图像解码装置和图像解码方法具有将过去被解码为图像的图像作为参考图像存储到帧存储器中的结构，其中参考图像中的顶行是 存储在顶部区域中，参考图像中的底线存储在底部区域中，以便使用过去解码的图像的一部分作为当前解码的图像中的参考块; 并且将参考图像中的最上面的最上面的行或最上面的行选择性地复制并存储在帧存储器中的顶部区域和底部区域中的参考图像中的最上面的顶部行和最上面的底部的区域，并且选择性地复印 并且将参考图像中的最下顶行或最下底行存储在帧存储器中的顶区域和底区中的参考图片中的最下顶行和最​​下底行下方的区域。

公开(公告)号：US07602319B2

公开(公告)日：2009-10-13

申请号：US12041395

申请日：2008-03-03

申请人： Tatsuhiro Suzumura ,  Shuji Michinaka ,  Kiwamu Watanabe ,  Satoshi Takekawa ,  Masashi Jobashi ,  Hiromitsu Nakayama ,  Yoshinori Shigeta ,  Takaya Ogawa ,  Akihiro Oue

发明人： Tatsuhiro Suzumura ,  Shuji Michinaka ,  Kiwamu Watanabe ,  Satoshi Takekawa ,  Masashi Jobashi ,  Hiromitsu Nakayama ,  Yoshinori Shigeta ,  Takaya Ogawa ,  Akihiro Oue

IPC分类号： H03M7/40

CPC分类号： H03M7/40 ,  H03M7/42 ,  H04N19/13

摘要： An image decoding apparatus having: a table selection controller configured to output a syntax selection signal which selects one of a prefix, a suffix, and a syntax; a variable length code decoding device configured to receive a bit stream, the syntax selection signal, and a suffix length, and, by using data contained in the bit stream and the suffix length, simultaneously decode the prefix and the suffix and output the result if the syntax selection signal selects the prefix 1 and the suffix, and decode the syntax and output the result if the syntax selection signal selects the syntax; a level formation device configured to receive the decoded prefix, the decoded suffix, and the decoded syntax, and form and output a level; and a suffix length updating device configured to receive the decoded prefix, the decoded suffix, and the decoded syntax, and update the suffix length.

摘要翻译： 一种图像解码装置，具有：表选择控制器，被配置为输出选择前缀，后缀和语法之一的语法选择信号; 被配置为接收比特流，语法选择信号和后缀长度的可变长度码解码装置，并且通过使用包含在比特流和后缀长度中的数据同时解码前缀和后缀并输出结果，如果 语法选择信号选择前缀1和后缀，并且如果语法选择信号选择语法，则对语法进行解码并输出结果; 电平形成装置，被配置为接收解码前缀，解码后缀和解码语法，并形成并输出电平; 以及后缀长度更新装置，被配置为接收解码的前缀，解码的后缀和解码的语法，并更新后缀长度。

公开(公告)号：US07567189B2

公开(公告)日：2009-07-28

申请号：US12027637

申请日：2008-02-07

申请人： Takaya Ogawa ,  Masashi Jobashi ,  Kiwamu Watanabe ,  Tatsuhiro Suzumura ,  Satoshi Takekawa ,  Hiromitsu Nakayama ,  Yoshinori Shigeta ,  Akihiro Oue ,  Shuji Michinaka

发明人： Takaya Ogawa ,  Masashi Jobashi ,  Kiwamu Watanabe ,  Tatsuhiro Suzumura ,  Satoshi Takekawa ,  Hiromitsu Nakayama ,  Yoshinori Shigeta ,  Akihiro Oue ,  Shuji Michinaka

IPC分类号： H03M7/40

CPC分类号： H03M7/40

摘要： When a combination between a plurality of FIFO memories and a variable length coding table is used, a load generated by an increase in number of FIFO memories serving as output destinations of a codeword length output from the variable length coding table when the codeword length is output is reduced. A variable length code decoding apparatus includes an input unit which receives variable length coding data, a plurality of FIFO memories which store the variable length coding data and output or update the variable length coding data on the basis of a codeword length of the variable length coding data, a FIFO input selecting unit which outputs the variable length coding data to one of the plurality of FIFO memories, a variable length coding table storing unit which stores a variable length coding table representing a relationship between the variable length coding data, the codeword length and a decoding value, reads the variable length coding data stored in one of the plurality of FIFO memories, and compares the read variable length coding data with the variable length coding table, a table selecting unit which determines the codeword length and the decoding value on the basis of a comparison result of the variable length coding table storing unit, and outputs the determined codeword length to one of the plurality of FIFO memories, and a control unit which selects one of the plurality of FIFO memories as a destination FIFO memory, reads the variable length coding data from the input unit or one of the unselected FIFO memories, and controls the FIFO input selecting unit such that the read variable length coding data is output to the selected FIFO memory.

摘要翻译： 当使用多个FIFO存储器和可变长度编码表之间的组合时，当输出码字长度时，由可变长度编码表输出的作为输出目的地的FIFO存储器的数量增加而产生的负载 降低了。 可变长度码解码装置包括接收可变长度编码数据的输入单元，存储可变长度编码数据的多个FIFO存储器，并且根据可变长度编码数据的码字长度输出或更新可变长度编码数据 数据，FIFO输入选择单元，其向多个FIFO存储器之一输出可变长度编码数据;可变长度编码表存储单元，其存储表示可变长度编码数据，码字长度之间的关系的可变长度编码表 和解码值，读取存储在多个FIFO存储器之一中的可变长度编码数据，并将读取的可变长度编码数据与可变长度编码表进行比较，确定代码字长度和解码值的表格选择单元 是可变长度编码表存储单元的比较结果的基础，并输出确定的码字 长度到多个FIFO存储器中的一个，以及选择多个FIFO存储器之一作为目的地FIFO存储器的控制单元，从输入单元或未选择的FIFO存储器之一读取可变长度编码数据，并且控制 FIFO输入选择单元，使得读取的可变长度编码数据被输出到所选择的FIFO存储器。

公开(公告)号：US20060202874A1

公开(公告)日：2006-09-14

申请号：US11166174

申请日：2005-06-27

申请人： Kiwamu Watanabe ,  Shuji Michinaka ,  Akihiro Oue ,  Tatsuhiro Suzumura ,  Satoshi Takekawa

发明人： Kiwamu Watanabe ,  Shuji Michinaka ,  Akihiro Oue ,  Tatsuhiro Suzumura ,  Satoshi Takekawa

IPC分类号： H03M7/40

CPC分类号： H03M7/40

摘要： A system for decoding a variable-length codeword includes a buffer circuit storing the codeword, a detection circuit detecting the number of bits of a prefix portion of the codeword by use of a detection table while updating the codeword, an extraction circuit extracting a codeword of a suffix portion of the codeword based on the number of bits of the prefix portion while updating the codeword, and a first decoding circuit decoding the codeword base on the number of bits of the prefix portion and the codeword of the suffix portion.

摘要翻译： 用于解码可变长度码字的系统包括存储码字的缓冲器电路，检测电路，在更新码字的同时利用检测表检测码字的前缀部分的比特数，提取电路提取码字的码字 在更新码字的同时基于前缀部分的比特数的码字的后缀部分，以及基于前缀部分的比特数和后缀部分的码字对码字进行解码的第一解码电路。

公开(公告)号：US07586426B2

公开(公告)日：2009-09-08

申请号：US12123793

申请日：2008-05-20

申请人： Kiwamu Watanabe ,  Shuji Michinaka ,  Tatsuhiro Suzumura ,  Hiromitsu Nakayama ,  Yoshinori Shigeta ,  Satoshi Takekawa ,  Masashi Jobashi ,  Takaya Ogawa ,  Akihiro Oue

发明人： Kiwamu Watanabe ,  Shuji Michinaka ,  Tatsuhiro Suzumura ,  Hiromitsu Nakayama ,  Yoshinori Shigeta ,  Satoshi Takekawa ,  Masashi Jobashi ,  Takaya Ogawa ,  Akihiro Oue

IPC分类号： H03M7/00

CPC分类号： H04N19/42 ,  H04N19/13

摘要： An image coding apparatus includes a variable length coding section, an arithmetic coding section and a common buffer memory. The variable length coding section inputs image data and outputs a binarized code sequence applied with variable length coding. The arithmetic coding section applies arithmetic coding to the binarized code sequence outputted from the variable length coding section. The common buffer memory transmits and receives data between the variable length coding section and the arithmetic coding section.

摘要翻译： 图像编码装置包括可变长度编码部分，算术编码部分和公共缓冲存储器。 可变长度编码部分输入图像数据并输出应用可变长度编码的二进制码序列。 算术编码部分对从可变长度编码部分输出的二进制码序列进行算术编码。 公共缓冲存储器在可变长度编码部分和算术编码部分之间发送和接收数据。

公开(公告)号：US20080291062A1

公开(公告)日：2008-11-27

申请号：US12123793

申请日：2008-05-20

申请人： Kiwamu Watanabe ,  Shuji Michinaka ,  Tatsuhiro Suzumura ,  Hiromitsu Nakayama ,  Yoshinori Shigeta ,  Satoshi Takekawa ,  Masashi Jobashi ,  Takaya Ogawa ,  Akihiro Oue

发明人： Kiwamu Watanabe ,  Shuji Michinaka ,  Tatsuhiro Suzumura ,  Hiromitsu Nakayama ,  Yoshinori Shigeta ,  Satoshi Takekawa ,  Masashi Jobashi ,  Takaya Ogawa ,  Akihiro Oue

IPC分类号： H03M7/34 ,  G06K9/36

CPC分类号： H04N19/42 ,  H04N19/13

摘要： An image coding apparatus includes a variable length coding section, an arithmetic coding section and a common buffer memory. The variable length coding section inputs image data and outputs a binarized code sequence applied with variable length coding. The arithmetic coding section applies arithmetic coding to the binarized code sequence outputted from the variable length coding section. The common buffer memory transmits and receives data between the variable length coding section and the arithmetic coding section.

摘要翻译： 图像编码装置包括可变长度编码部分，算术编码部分和公共缓冲存储器。 可变长度编码部分输入图像数据并输出应用可变长度编码的二进制码序列。 算术编码部分对从可变长度编码部分输出的二进制码序列进行算术编码。 公共缓冲存储器在可变长度编码部分和算术编码部分之间发送和接收数据。

公开(公告)号：US20060126743A1

公开(公告)日：2006-06-15

申请号：US11127225

申请日：2005-05-12

申请人： Satoshi Takekawa ,  Shuji Michinaka ,  Kiwamu Watanabe ,  Tatsuhiro Suzumura ,  Akihiro Oue

发明人： Satoshi Takekawa ,  Shuji Michinaka ,  Kiwamu Watanabe ,  Tatsuhiro Suzumura ,  Akihiro Oue

IPC分类号： H04N11/04 ,  H04B1/66 ,  H04N11/02 ,  H04N7/12

CPC分类号： H03M7/425 ,  H04N19/136 ,  H04N19/182 ,  H04N19/44 ,  H04N19/61 ,  H04N19/91

摘要： The present invention provides a moving picture format variable length code (VLC) decoder that decodes at a high speed. The VLC decoder includes an input data memory, which is stored with a pixel data coefficient string in moving picture format, a table reference device, which is stored with table reference data and receives memory data from the input data memory, table storage memory including a reference table, which is stored with parametric data, receives table reference data ARG from the table reference device, and transmits parametric data to the table reference device, and output data memory, which receives reference table data made from a coefficient flag output from the table reference device and the last coefficient flag.

摘要翻译： 本发明提供了以高速解码的运动图像格式可变长度码（VLC）解码器。 VLC解码器包括以运动图像格式存储的像素数据系数串的输入数据存储器，与参考数据一起存储的表参考设备，并从输入数据存储器接收存储器数据，表存储器包括 与参考数据一起存储的参考表从表参考装置接收表参考数据ARG，并将参数数据发送到表参考装置，并输出数据存储器，其接收从表中输出的系数标志产生的参考表数据 参考设备和最后一个系数标志。

公开(公告)号：US20080198046A1

公开(公告)日：2008-08-21

申请号：US12027637

申请日：2008-02-07

申请人： Takaya OGAWA ,  Masashi Jobashi ,  Kiwamu Watanabe ,  Tatsuhiro Suzumura ,  Satoshi Takekawa ,  Hiromitsu Nakayama ,  Yoshinori Shigeta ,  Akihiro Oue ,  Shuji Michinaka

发明人： Takaya OGAWA ,  Masashi Jobashi ,  Kiwamu Watanabe ,  Tatsuhiro Suzumura ,  Satoshi Takekawa ,  Hiromitsu Nakayama ,  Yoshinori Shigeta ,  Akihiro Oue ,  Shuji Michinaka

IPC分类号： H03M7/40

CPC分类号： H03M7/40

摘要： When a combination between a plurality of FIFO memories and a variable length coding table is used, a load generated by an increase in number of FIFO memories serving as output destinations of a codeword length output from the variable length coding table when the codeword length is output is reduced.A variable length code decoding apparatus includes an input unit which receives variable length coding data, a plurality of FIFO memories which store the variable length coding data and output or update the variable length coding data on the basis of a codeword length of the variable length coding data, a FIFO input selecting unit which outputs the variable length coding data to one of the plurality of FIFO memories, a variable length coding table storing unit which stores a variable length coding table representing a relationship between the variable length coding data, the codeword length and a decoding value, reads the variable length coding data stored in one of the plurality of FIFO memories, and compares the read variable length coding data with the variable length coding table, a table selecting unit which determines the codeword length and the decoding value on the basis of a comparison result of the variable length coding table storing unit, and outputs the determined codeword length to one of the plurality of FIFO memories, and a control unit which selects one of the plurality of FIFO memories as a destination FIFO memory, reads the variable length coding data from the input unit or one of the unselected FIFO memories, and controls the FIFO input selecting unit such that the read variable length coding data is output to the selected FIFO memory.

摘要翻译： 当使用多个FIFO存储器和可变长度编码表之间的组合时，当输出码字长度时，由可变长度编码表输出的作为输出目的地的FIFO存储器的数量增加而产生的负载 降低了。 可变长度码解码装置包括接收可变长度编码数据的输入单元，存储可变长度编码数据的多个FIFO存储器，并且根据可变长度编码数据的码字长度输出或更新可变长度编码数据 数据，FIFO输入选择单元，其向多个FIFO存储器之一输出可变长度编码数据;可变长度编码表存储单元，其存储表示可变长度编码数据，码字长度之间的关系的可变长度编码表 和解码值，读取存储在多个FIFO存储器之一中的可变长度编码数据，并将读取的可变长度编码数据与可变长度编码表进行比较，确定代码字长度和解码值的表格选择单元 是可变长度编码表存储单元的比较结果的基础，并输出确定的码字 长度到多个FIFO存储器中的一个，以及选择多个FIFO存储器之一作为目的地FIFO存储器的控制单元，从输入单元或未选择的FIFO存储器之一读取可变长度编码数据，并且控制 FIFO输入选择单元，使得读取的可变长度编码数据被输出到所选择的FIFO存储器。