公开(公告)号：US4796234A

公开(公告)日：1989-01-03

申请号：US927144

申请日：1986-11-05

申请人： Kiyoo Itoh ,  Yoshiki Kawajiri ,  Katsutaka Kimura ,  Ryoichi Hori ,  Jun Etoh

发明人： Kiyoo Itoh ,  Yoshiki Kawajiri ,  Katsutaka Kimura ,  Ryoichi Hori ,  Jun Etoh

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C8/12 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4091 ,  G11C7/00

CPC分类号： G11C8/14 ,  G11C11/4091 ,  G11C7/06 ,  G11C8/12

摘要： It is contemplated to realize a semiconductor memory with a large memory capacity, high in integration and low in power dissipation. A semiconductor memory is disclosed, comprising a plurality of blocks each having a memory cell array and sense amplifier(s) to differentially amplify signals read out from the array, wherein a common driving line of amplifiers composed of N-channel MOS transistors among said sense amplifiers and a common driving line of amplifiers composed of P-channel MOS transistors among the sense amplifers are connected between different blocks.

摘要翻译： 可以想到实现具有大存储容量，高集成度和低功耗的半导体存储器。 公开了一种半导体存储器，包括多个块，每个块具有存储单元阵列和读出放大器，用于差分放大从阵列读出的信号，其中由所述感测中的N沟道MOS晶体管组成的公共驱动线 放大器和由感测放大器中的P沟道MOS晶体管组成的放大器的公共驱动线连接在不同的块之间。

公开(公告)号：US07043466B2

公开(公告)日：2006-05-09

申请号：US09739758

申请日：2000-12-20

申请人： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

发明人： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

IPC分类号： G06N3/06 ,  G06N3/063 ,  G06N3/067 ,  G06N1/00 ,  G06F15/18

CPC分类号： G06N3/063

摘要： The neural network processing system according to the present invention includes a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operations of said memory circuit, said input/output circuit and said processing circuit.

摘要翻译： 根据本发明的神经网络处理系统包括存储电路，用于存储神经元输出值，连接权重，输出的期望值和学习所需的数据; 用于将数据写入或读出所述存储电路的输入/输出电路; 用于执行用于确定诸如存储在所述存储器电路中的数据的乘积，和和非线性转换的神经元输出，输出值与其期望值的比较以及学习所需的处理的处理的处理电路; 以及用于控制所述存储电路，所述输入/输出电路和所述处理电路的操作的控制电路。

公开(公告)号：US5875347A

公开(公告)日：1999-02-23

申请号：US723012

申请日：1996-09-30

申请人： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

发明人： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

IPC分类号： G06F15/18 ,  G06F17/16 ,  G06N3/04 ,  G06N3/063 ,  G06N99/00 ,  G06F15/00

CPC分类号： G06N3/063

摘要： Herein disclosed is a data processing system having a memory packaged therein for realizing a largescale and high-speed parallel distributed processing and, especially, a data processing system for the neural network processing. The neural network processing system according to the present invention comprises: a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operations of said memory circuit, said input/output circuit and said processing circuit. The processing circuit is constructed to include at least one of an adder, a multiplier, a nonlinear transfer function circuit and a comparator so that at least a portion of the processing necessary for determining the neutron output values such as the product or sum may be accomplished in parallel. Moreover, these circuits are shared among a plurality of neutrons and are operated in a time sharing manner to determine the plural neuron output values. Still moreover, the aforementioned comparator compares the neuron output value determined and the desired value of the output in parallel.

摘要翻译： 这里公开了一种数据处理系统，其中封装有用于实现大规模和高速并行分布式处理的存储器，特别是用于神经网络处理的数据处理系统。 根据本发明的神经网络处理系统包括：存储电路，用于存储神经元输出值，连接权重，输出的期望值和学习所需的数据; 用于将数据写入或读出所述存储电路的输入/输出电路; 用于执行用于确定诸如存储在所述存储器电路中的数据的乘积，和和非线性转换的神经元输出，输出值与其期望值的比较以及学习所需的处理的处理的处理电路; 以及用于控制所述存储电路，所述输入/输出电路和所述处理电路的操作的控制电路。 处理电路被构造为包括加法器，乘法器，非线性传递函数电路和比较器中的至少一个，使得可以实现用于确定诸如乘积或和的中子输出值所需的处理的至少一部分 在平行下。 此外，这些电路在多个中子之间共享并且以分时方式操作以确定多个神经元输出值。 此外，上述比较器并行地比较所确定的神经元输出值和输出的期望值。

公开(公告)号：US5165009A

公开(公告)日：1992-11-17

申请号：US634046

申请日：1990-12-26

申请人： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

发明人： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

IPC分类号： G06F15/18 ,  G06F17/16 ,  G06N3/04 ,  G06N3/063 ,  G06N99/00

CPC分类号： G06N3/063

摘要： Herein disclosed is a data processing system having a memory packaged therein for realizing a large-scale and high-speed parallel distributed processing and, especially, a data processing system for the neural network processing. The neural network processing system according to the present invention comprises: a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; and input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operations of said memory circuit, said input/output circuit and said processing circuit. The processing circuit is constructed to include at least one of an adder, a multiplier, a nonlinear transfer function circuit and a comparator so that at least a portion of the processing necessary for determining the neutron output values such as the product or sum may be accomplished in parallel. Moreover, these circuits are shared among a plurality of neutrons and are operated in a time sharing manner to determine the plural neuron output values. Still moreover, the aforementioned comparator compares the neuron output value determined and the desired value of the otuput in parallel.

公开(公告)号：US5594916A

公开(公告)日：1997-01-14

申请号：US369163

申请日：1995-01-04

申请人： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

发明人： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

IPC分类号： G06F15/18 ,  G06F17/16 ,  G06N3/04 ,  G06N3/063 ,  G06N99/00 ,  G06F9/00

CPC分类号： G06N3/063

摘要： A data processing system has a memory for realizing large-scale and high-speed parallel distributed processing and, especially, a data processing system for neural network processing. The neural network processing system comprises: a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operation of the memory circuit, the input/output circuit and the processing circuit. The processing circuit includes at least one of an address, a multiplier, a nonlinear transfer function circuit and a comparator so that at least a portion of the processing necessary for determining the neuron output values such as the product of sum may be accomplished in parallel. Moreover, these circuits are shared among a plurality of neurons and are operated in a time sharing manner to determine the plural neuron output values. Still moreover, the aforementioned comparator compares the neuron output value determined and the desired value of the output in parallel.

摘要翻译： 数据处理系统具有用于实现大规模高速并行分布式处理的存储器，特别是用于神经网络处理的数据处理系统。 神经网络处理系统包括：存储电路，用于存储神经元输出值，连接权重，输出的期望值和学习所需的数据; 用于将数据写入或读出所述存储电路的输入/输出电路; 用于执行用于确定诸如存储在所述存储器电路中的数据的乘积，和和非线性转换的神经元输出，输出值与其期望值的比较以及学习所需的处理的处理的处理电路; 以及用于控制存储电路，输入/输出电路和处理电路的操作的控制电路。 处理电路包括地址，乘法器，非线性传递函数电路和比较器中的至少一个，使得可以并行实现用于确定神经元输出值（例如和乘积）所必需的处理的至少一部分。 此外，这些电路在多个神经元之间共享并且以分时方式操作以确定多个神经元输出值。 此外，上述比较器并行地比较所确定的神经元输出值和输出的期望值。

公开(公告)号：US5426757A

公开(公告)日：1995-06-20

申请号：US938755

申请日：1992-09-01

申请人： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

发明人： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

IPC分类号： G06F15/18 ,  G06F17/16 ,  G06N3/04 ,  G06N3/063 ,  G06N99/00 ,  G06F15/16

CPC分类号： G06N3/063

摘要： Herein disclosed is a data processing system having a memory packaged therein for realizing a large-scale and high-speed parallel distributed processing and, especially, a data processing system for the neural network processing. The neural network processing system according to the present invention comprises: a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operations of said memory circuit, said input/output circuit and said processing circuit. The processing circuit is constructed to include at least one of an adder, a multiplier, a nonlinear transfer function circuit and a comparator so that at least a portion of the processing necessary for determining the neutron output values such as the product or sum may be accomplished in parallel. Moreover, these circuits are shared among a plurality of neutrons and are operated in a time sharing manner to determine the plural neuron output values. Still moreover, the aforementioned comparator compares the neuron output value determined and the desired value of the output in parallel.

摘要翻译： 这里公开了一种数据处理系统，其中封装有用于实现大规模和高速并行分布式处理的存储器，特别是用于神经网络处理的数据处理系统。 根据本发明的神经网络处理系统包括：存储电路，用于存储神经元输出值，连接权重，输出的期望值和学习所需的数据; 用于将数据写入或读出所述存储电路的输入/输出电路; 用于执行用于确定诸如存储在所述存储器电路中的数据的乘积，和和非线性转换的神经元输出，输出值与其期望值的比较以及学习所需的处理的处理的处理电路; 以及用于控制所述存储电路，所述输入/输出电路和所述处理电路的操作的控制电路。 处理电路被构造为包括加法器，乘法器，非线性传递函数电路和比较器中的至少一个，使得可以实现用于确定诸如乘积或和的中子输出值所需的处理的至少一部分 在平行下。 此外，这些电路在多个中子之间共享并且以分时方式操作以确定多个神经元输出值。 此外，上述比较器并行地比较所确定的神经元输出值和输出的期望值。

公开(公告)号：US06205556B1

公开(公告)日：2001-03-20

申请号：US09198658

申请日：1998-11-24

申请人： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

发明人： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

IPC分类号： G06F126

CPC分类号： G06N3/063

摘要： Herein disclosed is a data processing system having a memory packaged therein for realizing a large-scale and high-speed parallel distributed processing and, especially, a data processing system for the neural network processing. The neural network processing system according to the present invention comprises: a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operations of said memory circuit, said input/output circuit and said processing circuit. The processing circuit is constructed to include at least one of an adder, a multiplier, a nonlinear transfer function circuit and a comparator so that at least a portion of the processing necessary for determining the neutron output values such as the product or sum may be accomplished in parallel. Moreover, these circuits are shared among a plurality of neutrons and are operated in a time sharing manner to determine the plural neuron output values. Still moreover, the aforementioned comparator compares the neuron output value determined and the desired value of the output in parallel.

摘要翻译： 这里公开了一种数据处理系统，其中封装有用于实现大规模和高速并行分布式处理的存储器，特别是用于神经网络处理的数据处理系统。 根据本发明的神经网络处理系统包括：存储电路，用于存储神经元输出值，连接权重，输出的期望值和学习所需的数据; 用于将数据写入或读出所述存储电路的输入/输出电路; 用于执行用于确定诸如存储在所述存储器电路中的数据的乘积，和和非线性转换的神经元输出，输出值与其期望值的比较以及学习所需的处理的处理的处理电路; 以及用于控制所述存储电路，所述输入/输出电路和所述处理电路的操作的控制电路。 处理电路被构造为包括加法器，乘法器，非线性传递函数电路和比较器中的至少一个，使得可以实现用于确定诸如乘积或和的中子输出值所需的处理的至少一部分 在平行下。 此外，这些电路在多个中子之间共享并且以分时方式操作以确定多个神经元输出值。 此外，上述比较器并行地比较所确定的神经元输出值和输出的期望值。

公开(公告)号：US4930112A

公开(公告)日：1990-05-29

申请号：US934546

申请日：1986-11-24

申请人： Hitoshi Tanaka ,  Ryoichi Hori ,  Kiyoo Itoh ,  Katsutaka Kimura ,  Katsuhiro Shimohigashi

发明人： Hitoshi Tanaka ,  Ryoichi Hori ,  Kiyoo Itoh ,  Katsutaka Kimura ,  Katsuhiro Shimohigashi

IPC分类号： G11C11/407 ,  G05F1/46 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/409

CPC分类号： G05F1/465 ,  G11C11/4074

摘要： A semiconductor device comprising a plurality of circuits driven by at least one external power source, and at least one voltage converter transforming the voltage of the external power source into another voltage. At least a part of the plurality of circuits are driven by the output voltage of the at least one voltage converter, which is provided with a controller for controlling its load driving power, corresponding to the operation of the part of the plurality of circuits. The voltage converter includes a voltage limiter which is used exclusively for each of the different natures of the loads, and its operation and load driving power are controlled, depending on the operations of each of the loads.

摘要翻译： 一种半导体器件，包括由至少一个外部电源驱动的多个电路和至少一个将外部电源的电压转换成另一电压的电压转换器。 所述多个电路的至少一部分由所述至少一个电压转换器的输出电压驱动，所述至少一个电压转换器的输出电压与所述多个电路的所述部分的操作相对应地设置有用于控制其负载驱动功率的控制器。 电压转换器包括专用于负载的不同性质的电压限制器，并且根据每个负载的操作来控制其操作和负载驱动功率。

公开(公告)号：US4894696A

公开(公告)日：1990-01-16

申请号：US938967

申请日：1986-12-08

申请人： Eiji Takeda ,  Kiyoo Itoh ,  Ryoichi Hori ,  Katsuhiro Shimohigashi ,  Katsutaka Kimura

发明人： Eiji Takeda ,  Kiyoo Itoh ,  Ryoichi Hori ,  Katsuhiro Shimohigashi ,  Katsutaka Kimura

IPC分类号： H01L27/10 ,  G11C11/34 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10861 ,  Y10S257/90

摘要： A very highly integrated semiconductor memory which enables the dynamic random access memory to develop less soft error and to eliminate margin for aligning the masks, that hinders the device from being highly integrated. The memory cell capacitor is constituted by a trench which is provided at a position defined by an insulator formed on the side of gate electrode of a MOS transistor that constitutes the memory cell. Therefore, the MOS transistor and the trench capacitor are self-aligned, and no margin is required for alignment.

摘要翻译： 一种非常高度集成的半导体存储器，其使得动态随机存取存储器能够开发更少的软错误并消除对准掩模的余量，这妨碍了器件的高度集成。 存储单元电容器由设置在由形成在构成存储单元的MOS晶体管的栅极侧的绝缘体限定的位置处的沟槽构成。 因此，MOS晶体管和沟槽电容器是自对准的，并且不需要用于对准的余量。

公开(公告)号：US07345938B2

公开(公告)日：2008-03-18

申请号：US11797984

申请日：2007-05-09

申请人： Riichiro Takemura ,  Kiyoo Itoh ,  Tomonori Sekiguchi ,  Takeshi Sakata ,  Katsutaka Kimura

发明人： Riichiro Takemura ,  Kiyoo Itoh ,  Tomonori Sekiguchi ,  Takeshi Sakata ,  Katsutaka Kimura

IPC分类号： G11C7/00

CPC分类号： G11C7/065 ,  G11C5/025 ,  G11C5/14 ,  G11C7/06 ,  G11C7/08 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4091 ,  G11C2207/065 ,  H01L27/0207 ,  H01L27/10894

摘要： A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a plurality of drive switches for restore operation are concentratively disposed at one end of a row of the sense amplifiers. A potential for over-driving is supplied using a meshed power line circuit. Through the use of the drive switches for over-driving, initial sense operation can be performed on data line pairs with a voltage having an amplitude larger than a data-line amplitude, allowing implementation of high-speed sense operation. The distributed arrangement of the drive switched for over-driving makes it possible to dispersively supply current in sense operation, thereby reducing a difference in sense voltage with respect to far and near positions of the sense amplifiers.

摘要翻译： 一种读出放大器即使在存储器阵列电压降低的情况下，也能够使用来自存储单元的微小信号，以较低的功耗进行高速数据检测操作。 用于过驱动的多个驱动开关被分布地布置在感测放大器区域中，并且用于恢复操作的多个驱动开关被集中地布置在一行的读出放大器的一端。 使用网状电力线电路提供过驱动的可能性。 通过使用用于过驱动的驱动开关，可以利用具有大于数据线幅度的电压的数据线对执行初始感测操作，从而实现高速感测操作。 驱动器的分布布置使得用于过驱动的驱动器能够在感测操作中分散地提供电流，从而减小感测放大器的远和近位置的感测电压的差异。