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1.发明授权System for directly and indirectly accessing control registers by different operating systems based upon value of operating system indication bit 失效基于操作系统指示位的值，由不同操作系统直接和间接访问控制寄存器的系统
公开(公告)号：US4835677A
公开(公告)日：1989-05-30
申请号：US8155
申请日：1987-01-21
CPC分类号： G06F9/4843 , G06F9/45533
摘要： A data processing system comprising at least two operating systems (OS1, OS2) for virtual machines, a supervisory operating system, i.e., a control program (CP) for controlling the operating systems, control registers (CR0, CR1, ---) and an extended control register (ECR) having a special bit. When a control register operating instruction (LCTL or STCTL) is executed by one of the operating systems, the special bit has a first value and the operating system directly accesses the control register. When the other of the operating systems attempts to execute such a control register operating instruction, the special bit has a second value and an interruption is generated in the supervisory operating system.
摘要翻译： 一种数据处理系统，包括用于虚拟机的至少两个操作系统（OS1，OS2），监控操作系统，即用于控制操作系统的控制程序（CP），控制寄存器（CR0，CR1，...）和 具有特殊位的扩展控制寄存器（ECR）。 当控制寄存器操作指令（LCTL或STCTL）由其中一个操作系统执行时，特殊位具有第一个值，操作系统直接访问控制寄存器。 当另一个操作系统试图执行这样的控制寄存器操作指令时，特殊位具有第二值，并且在监控操作系统中产生中断。
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公开(公告)号：US4623962A
公开(公告)日：1986-11-18
申请号：US509609
申请日：1983-06-30
CPC分类号： G06F9/30043 , G06F9/30101 , G06F9/30138 , G06F9/30189 , G06F9/34
摘要： This invention relates to a register and more specifically to register control in a data processing system. In general, a number of control registers are theoretically required that is less than the maximum number which can be designated, and only the required number of registers are mounted as hardware. In order to add functions or to provide compatibility with other systems, it is sometimes required to use a register that is not mounted as hardware, or to use the registers mounted as hardware for conflicting purposes. Virtual registers are accordingly provided for at address locations in the memory of the processing system. However, if only the registers to be added are thusly provided for in the memory, the instructions must be executed by distinguishing between register access and memory access, in accordance with register number, etc. Thus, this invention provides a number of virtual registers for instance equal to the number that can be designated. The controls are thereby simplified in accordance with the kind of instruction to be performed. Namely, when an instruction is the LOAD instruction, the same content is loaded into both real an virtual registers from a respective address of the memory, and when it is the STORE instruction, the content from a respective virtual register is stored into the respective address of the memory.
摘要翻译： 本发明涉及一种寄存器，更具体地涉及数据处理系统中的寄存器控制。 一般来说，理论上要求数量少于可指定的最大数量的控制寄存器，只有所需数量的寄存器作为硬件进行安装。 为了添加功能或提供与其他系统的兼容性，有时需要使用未作为硬件安装的寄存器，或者使用作为硬件安装的寄存器用于冲突的目的。 相应地，在处理系统的存储器中的地址位置提供虚拟寄存器。 然而，如果仅在存储器中提供要添加的寄存器，则必须通过根据寄存器号等区分寄存器访问和存储器访问来执行指令。因此，本发明提供了许多虚拟寄存器，用于 实例等于可以指定的数字。 因此，根据要执行的指令的种类，简化了控制。 也就是说，当指令是LOAD指令时，相同的内容从存储器的相应地址加载到虚拟寄存器两者中，并且当它是存储指令时，来自相应虚拟寄存器的内容被存储到相应的地址 的记忆。
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公开(公告)号：US4566062A
公开(公告)日：1986-01-21
申请号：US508503
申请日：1983-06-28
CPC分类号： G06F9/30079 , G06F9/223 , G06F9/226 , G06F9/3869
摘要： This invention relates to a timing control, for example, a control for reserving a waiting time when a data processor sends or receives data to or from an external device. Dummy cycles for a number of cycles having a processing time equal to the desired waiting time are generated by a dummy instruction. A timing control system is disclosed which is especially suitable for a micro-program system of a pipeline control system.
摘要翻译： 本发明涉及定时控制，例如，当数据处理器向外部设备发送或接收数据时，用于保留等待时间的控制。 通过虚拟指令产生具有等于期望等待时间的处理时间的多个周期的虚拟周期。 公开了一种特别适用于管道控制系统的微程序系统的定时控制系统。
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4.发明授权Data processing system for preventing machine stoppage due to an error in a copy register 失效数据处理系统，用于防止复制寄存器中的错误导致机器停机
公开(公告)号：US4594710A
公开(公告)日：1986-06-10
申请号：US561965
申请日：1983-12-15
CPC分类号： G06F11/141
摘要： A data processing system comprising an instruction control unit for controlling system operation, a storage control unit for storing data used for the system operation, and a machine check interruption portion for carrying out a machine check interruption when an error occurs during the system operation. The instruction control unit has a system control register group for storing system control data. The storage control unit has a copy register group for storing data copied from the system control data. The instruction control unit further comprises a register save state portion for copying the contents stored in the system control register group into the copy register group during the machine check interruption when an error occurs in the copy register group during the system operation. In this manner, a machine stop due to an error only in the copy register group, is prevented.
摘要翻译： 一种数据处理系统，包括用于控制系统操作的指令控制单元，用于存储用于系统操作的数据的存储控制单元和用于在系统操作期间发生错误时执行机器检查中断的机器检查中断部分。 指令控制单元具有用于存储系统控制数据的系统控制寄存器组。 存储控制单元具有用于存储从系统控制数据复制的数据的复制寄存器组。 指令控制单元还包括寄存器保存状态部分，用于在系统操作期间在复制寄存器组中发生错误时，在机器检查中断期间将存储在系统控制寄存器组中的内容复制到复制寄存器组中。 以这种方式，由于仅在复制寄存器组中的错误而停止机器。
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公开(公告)号：US4566103A
公开(公告)日：1986-01-21
申请号：US534134
申请日：1983-09-20
申请人： Kiyosumi Sato , Kazuyuki Shimizu
发明人： Kiyosumi Sato , Kazuyuki Shimizu
CPC分类号： G06F11/141
摘要： An erroneous microinstruction and related preceding microinstructions are subjected to a so-called retry operation so as to restore the microprogram-controlled unit and correct the error. The retry operation is carried out under an interlock mode, in which both detection and correction occur prior to processing for each microinstruction. At the same time, an address specifying a thus detected erroneous microinstruction is recorded. When the recorded address is next generated, the interlock mode is automatically entered for the erroneous microstruction only.
摘要翻译： 对错误的微指令和相关的前述微指令进行所谓的重试操作，以恢复微程序控制单元并纠正错误。 重试操作在互锁模式下进行，其中在对每个微指令进行处理之前都进行检测和校正。 同时，记录指定如此检测到的错误微指令的地址。 当记录的地址下一个生成时，自动输入互锁模式用于错误的微量构造。
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