公开(公告)号：US4835677A

公开(公告)日：1989-05-30

申请号：US8155

申请日：1987-01-21

申请人： Kiyosumi Sato ,  Yoshihiro Mizushima ,  Katsumi Ohnishi ,  Motokazu Kato ,  Toshio Matsumoto

发明人： Kiyosumi Sato ,  Yoshihiro Mizushima ,  Katsumi Ohnishi ,  Motokazu Kato ,  Toshio Matsumoto

IPC分类号： G06F9/46 ,  G06F9/22 ,  G06F9/455 ,  G06F9/48 ,  G06F12/08

CPC分类号： G06F9/4843 ,  G06F9/45533

摘要： A data processing system comprising at least two operating systems (OS1, OS2) for virtual machines, a supervisory operating system, i.e., a control program (CP) for controlling the operating systems, control registers (CR0, CR1, ---) and an extended control register (ECR) having a special bit. When a control register operating instruction (LCTL or STCTL) is executed by one of the operating systems, the special bit has a first value and the operating system directly accesses the control register. When the other of the operating systems attempts to execute such a control register operating instruction, the special bit has a second value and an interruption is generated in the supervisory operating system.

摘要翻译： 一种数据处理系统，包括用于虚拟机的至少两个操作系统（OS1，OS2），监控操作系统，即用于控制操作系统的控制程序（CP），控制寄存器（CR0，CR1，...）和 具有特殊位的扩展控制寄存器（ECR）。 当控制寄存器操作指令（LCTL或STCTL）由其中一个操作系统执行时，特殊位具有第一个值，操作系统直接访问控制寄存器。 当另一个操作系统试图执行这样的控制寄存器操作指令时，特殊位具有第二值，并且在监控操作系统中产生中断。

公开(公告)号：US4623962A

公开(公告)日：1986-11-18

申请号：US509609

申请日：1983-06-30

申请人： Toshio Matsumoto ,  Motokazu Kato ,  Kiyosumi Sato ,  Yoshihiro Mizushima ,  Katsumi Ohnishi

发明人： Toshio Matsumoto ,  Motokazu Kato ,  Kiyosumi Sato ,  Yoshihiro Mizushima ,  Katsumi Ohnishi

IPC分类号： G06F12/00 ,  G06F9/30 ,  G06F9/312 ,  G06F9/318 ,  G06F9/34 ,  G06F9/455 ,  G06F9/46 ,  G06F9/00

CPC分类号： G06F9/30043 ,  G06F9/30101 ,  G06F9/30138 ,  G06F9/30189 ,  G06F9/34

摘要： This invention relates to a register and more specifically to register control in a data processing system. In general, a number of control registers are theoretically required that is less than the maximum number which can be designated, and only the required number of registers are mounted as hardware. In order to add functions or to provide compatibility with other systems, it is sometimes required to use a register that is not mounted as hardware, or to use the registers mounted as hardware for conflicting purposes. Virtual registers are accordingly provided for at address locations in the memory of the processing system. However, if only the registers to be added are thusly provided for in the memory, the instructions must be executed by distinguishing between register access and memory access, in accordance with register number, etc. Thus, this invention provides a number of virtual registers for instance equal to the number that can be designated. The controls are thereby simplified in accordance with the kind of instruction to be performed. Namely, when an instruction is the LOAD instruction, the same content is loaded into both real an virtual registers from a respective address of the memory, and when it is the STORE instruction, the content from a respective virtual register is stored into the respective address of the memory.

摘要翻译： 本发明涉及一种寄存器，更具体地涉及数据处理系统中的寄存器控制。 一般来说，理论上要求数量少于可指定的最大数量的控制寄存器，只有所需数量的寄存器作为硬件进行安装。 为了添加功能或提供与其他系统的兼容性，有时需要使用未作为硬件安装的寄存器，或者使用作为硬件安装的寄存器用于冲突的目的。 相应地，在处理系统的存储器中的地址位置提供虚拟寄存器。 然而，如果仅在存储器中提供要添加的寄存器，则必须通过根据寄存器号等区分寄存器访问和存储器访问来执行指令。因此，本发明提供了许多虚拟寄存器，用于 实例等于可以指定的数字。 因此，根据要执行的指令的种类，简化了控制。 也就是说，当指令是LOAD指令时，相同的内容从存储器的相应地址加载到虚拟寄存器两者中，并且当它是存储指令时，来自相应虚拟寄存器的内容被存储到相应的地址 的记忆。

公开(公告)号：US4654779A

公开(公告)日：1987-03-31

申请号：US534125

申请日：1983-09-20

申请人： Motokazu Kato ,  Toshio Matsumoto

发明人： Motokazu Kato ,  Toshio Matsumoto

IPC分类号： G06F9/28 ,  G06F9/22 ,  G06F9/30 ,  G06F9/455 ,  G06F9/46 ,  G06F12/14 ,  G06F15/16 ,  G06F15/167 ,  G06F15/177 ,  G06F12/00 ,  G06F9/00 ,  G06F9/06

CPC分类号： G06F9/463 ,  G06F12/1466

摘要： A multiprocessor system including firmware, which system is comprised of at least a plurality of central processing units and a main memory to be commonly occupied by all the central processing units. The main memory is composed of an operating system area and a firmware area. The firmware area is divided into a common firmware area utilized by all the central processing units and a plurality of independent prefix areas allotted to the central processing units. Each prefix area is operative as an interface port, for a respective central processing unit, between the operating system area and the common firmware area.

摘要翻译： 包括固件的多处理器系统，该系统由至少多个中央处理单元和由所有中央处理单元共同占用的主存储器组成。 主存储器由操作系统区域和固件区域组成。 固件区域被分为由所有中央处理单元使用的公共固件区域和分配给中央处理单元的多个独立前缀区域。 每个前缀区域对于相应的中央处理单元在操作系统区域和公共固件区域之间用作接口端口。

公开(公告)号：US4598402A

公开(公告)日：1986-07-01

申请号：US549462

申请日：1983-11-07

申请人： Toshio Matsumoto ,  Motokazu Kato

发明人： Toshio Matsumoto ,  Motokazu Kato

IPC分类号： G06F12/16 ,  G06F11/10 ,  G06F12/08 ,  G11C29/00

CPC分类号： G11C29/88 ,  G06F11/1064

摘要： In a data processing device comprising a main storage unit, a buffer storage unit, and an error check and correction circuit, when data held in the buffer storage unit contains a single-bit error, the data containing the single-bit error is moved out from the buffer storage unit by generating a predetermined number of addresses having the same number (memory sector) as the data containing the single-bit error. The data is then corrected by the error check and correction circuit, and the corrected data is stored in the main storage unit.

摘要翻译： 在包括主存储单元，缓冲存储单元和错误检查和校正电路的数据处理设备中，当保存在缓冲存储单元中的数据包含单位错误时，将包含单位错误的数据移出 通过产生具有与包含单位错误的数据相同数量（存储器扇区）的预定数量的地址从缓冲存储单元。 然后通过错误检查和校正电路校正数据，并且校正的数据被存储在主存储单元中。

公开(公告)号：US4587654A

公开(公告)日：1986-05-06

申请号：US554730

申请日：1983-11-23

申请人： Toshio Matsumoto ,  Motokazu Kato

发明人： Toshio Matsumoto ,  Motokazu Kato

IPC分类号： G06F11/00 ,  G06F11/07

CPC分类号： G06F11/0721 ,  G06F11/0751 ,  G06F11/0793

摘要： A system for processing machine check interruption using a data processor which outputs a machine check interruption signal by detecting the generation of a machine check condition and which performs interruption processing on the basis of the machine check interruption signal. The data processor includes a specific code detector which detects a specific interruption signal among the machine check interruption signals, a signal converting circuit for converting the machine check interruption signal into a modified code signal when the interruption signal generated by the machine check interruption is the above-mentioned specific code, and a control portion which assumes a disabled-waiting condition in response to the modified code signal. The operation of the data processor is stopped by placing the control portion in a disabled-waiting condition when interruption of the above-mentioned specific code occurs.

摘要翻译： 一种使用数据处理器处理机器检查中断的系统，其通过检测机器检查条件的生成并基于机器检查中断信号执行中断处理来输出机器检查中断信号。 数据处理器包括检测机器检查中断信号中的特定中断信号的特定代码检测器，当机器检查中断产生的中断信号为上述时，将机器检查中断信号转换为修改代码信号的信号转换电路 以及响应于修改的代码信号而呈现禁用等待状态的控制部分。 当发生上述特定代码的中断时，通过将控制部分置于禁用等待状态来停止数据处理器的操作。

公开(公告)号：US4601008A

公开(公告)日：1986-07-15

申请号：US509610

申请日：1983-06-30

申请人： Motokazu Kato

发明人： Motokazu Kato

IPC分类号： G06F11/22 ,  G06F11/24 ,  G06F11/34

CPC分类号： G06F11/348

摘要： A data processing system having a performance measurement system which is capable of setting desired performance measurement items. In the performance measuring system an interrupt by internal timer is used for triggering performance measurement, the performance measurement system executes the processings after this timer interrupt, and processing results for each measurement item are collected in the main storage.

摘要翻译： 一种数据处理系统，具有能够设定所需性能测量项目的性能测量系统。 在性能测量系统中，内部定时器的中断用于触发性能测量，性能测量系统执行此定时器中断后的处理，每个测量项目的处理结果都收集在主存储器中。