-
公开(公告)号：US07821849B2
公开(公告)日：2010-10-26
申请号：US12028302
申请日：2008-02-08
IPC分类号： G11C7/10
CPC分类号： G06F17/5045
摘要： A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support different memory modules, identification signals are provided from the memory modules or an identification module to configure the core portion.
摘要翻译： 可配置的处理器架构使用多个处理器配置的通用模拟数据库来降低生产定制处理器配置的成本。 在每个处理器配置中使用不变的核心部分。 为了支持不同的存储器模块，从存储器模块或识别模块提供识别信号以配置核心部分。
-
公开(公告)号：US07281228B2
公开(公告)日：2007-10-09
申请号：US10777863
申请日：2004-02-11
申请人： Klaus J. Oberlaender , Ralph Haines
发明人： Klaus J. Oberlaender , Ralph Haines
IPC分类号： G06F17/50
CPC分类号： G06F15/7846 , G06F17/5045
摘要： An embedded processor architecture includes a processing core with configurable memory system. Memory components can be inserted, omitted and resized in different configuration of the memory system without causing irregular features that may cause wasted silicon area. Furthermore, all the various configurations of the memory system are designed to interface with the processing core so that the processing core can be reused without change.
摘要翻译： 嵌入式处理器架构包括具有可配置存储器系统的处理核心。 可以在存储器系统的不同配置中插入，省略和调整存储器组件，而不会引起可能导致浪费硅面积的不规则特征。 此外，存储器系统的所有各种配置被设计为与处理核心接口，使得可以不改变地重复使用处理核心。
-
公开(公告)号：US07339837B2
公开(公告)日：2008-03-04
申请号：US10848997
申请日：2004-05-18
IPC分类号： G11C7/10
CPC分类号： G06F17/5045
摘要： A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support different memory modules, identification signals are provided from the memory modules or an identification module to configure the core portion.
摘要翻译： 可配置的处理器架构使用多个处理器配置的通用模拟数据库来降低生产定制处理器配置的成本。 在每个处理器配置中使用不变的核心部分。 为了支持不同的存储器模块，从存储器模块或识别模块提供识别信号以配置核心部分。
-
公开(公告)号：US08270231B2
公开(公告)日：2012-09-18
申请号：US12912336
申请日：2010-10-26
IPC分类号： G11C7/10
CPC分类号： G06F17/5045
摘要： A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support different memory modules, identification signals are provided from the memory modules or an identification module to configure the core portion.
摘要翻译： 可配置的处理器架构使用多个处理器配置的通用模拟数据库来降低生产定制处理器配置的成本。 在每个处理器配置中使用不变的核心部分。 为了支持不同的存储器模块，从存储器模块或识别模块提供识别信号以配置核心部分。
-
公开(公告)号：US07366819B2
公开(公告)日：2008-04-29
申请号：US10777710
申请日：2004-02-11
申请人： Klaus J. Oberlaender
发明人： Klaus J. Oberlaender
CPC分类号： G06F12/0886 , G06F1/32 , G06F12/0846 , G06F2212/1028 , Y02D10/13
摘要： A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple cache lines. Because each tower can be addressed independently and the cache lines are split among the towers, unaligned cache access can be performed. Furthermore, power can be conserved because not all the memory towers of the cache unit needs to be activated during some memory access operations.
摘要翻译： 一个高速缓存单元多个内存塔，可独立寻址。 高速缓存行分为多个塔。 此外，存储塔的物理线路由多条高速缓存行共享。 因为可以独立地寻址每个塔，并且高速缓存行在塔之间分割，所以可以执行未对齐的高速缓存访问。 此外，可以节省功率，因为在某些存储器访问操作期间不需要激活高速缓存单元的所有存储塔。
-
公开(公告)号：US08407392B2
公开(公告)日：2013-03-26
申请号：US13324917
申请日：2011-12-13
申请人： Klaus J. Oberlaender
发明人： Klaus J. Oberlaender
CPC分类号： G06F12/0886 , G06F1/32 , G06F12/0846 , G06F2212/1028 , Y02D10/13
摘要： A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple cache lines. Because each tower can be addressed independently and the cache lines are split among the towers, unaligned cache access can be performed. Furthermore, power can be conserved because not all the memory towers of the cache unit needs to be activated during some memory access operations.
摘要翻译： 一个高速缓存单元多个内存塔，可独立寻址。 高速缓存行分为多个塔。 此外，存储塔的物理线路由多条高速缓存行共享。 因为可以独立地寻址每个塔，并且高速缓存行在塔之间分割，所以可以执行未对齐的高速缓存访问。 此外，可以节省功率，因为在某些存储器访问操作期间不需要激活高速缓存单元的所有存储塔。
-
公开(公告)号：US07437692B2
公开(公告)日：2008-10-14
申请号：US10705101
申请日：2003-11-10
申请人： Klaus J. Oberlaender
发明人： Klaus J. Oberlaender
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A simulation/debugging method for SOC designs that utilizes initial memory values loaded into a simulation model. A test program is then executed, and incremetal transaction records are generated for each incremental memory access (e.g., data write operations). Each transaction record includes a timestamp, address and data values. The transaction record information is stored/captured on a high level-based (i.e., system address-based) domain that takes into account all the tiling, interleaving, scrambling, and unaligned accessing used in the simulated SOC design, rather than on a low level-based (i.e., physical memory address-based) domain. Upon completing the simulation, the instantaneous memory contents at any selected point in time during the simulated execution are calculated by combining the initial data and intermediate transaction record information. Automatic memory dump and sanity check tests verify the integrity of the final data value and incremental transactions. Cache memory information is collected and displayed using a system-level format.
摘要翻译： 一种利用加载到仿真模型中的初始存储器值的SOC设计的仿真/调试方法。 然后执行测试程序，并为每个增量存储器访问（例如，数据写入操作）生成增量事务记录。 每个事务记录都包含时间戳，地址和数据值。 交易记录信息被存储/捕获在考虑到模拟SOC设计中使用的所有平铺，交织，加扰和非对准访问的高级（即，基于系统地址的）域上，而不是低 （即基于物理内存地址的）域。 在完成仿真之后，通过组合初始数据和中间交易记录信息来计算模拟执行期间任何选定时间点的瞬时存储器内容。 自动内存转储和完整性检查测试验证最终数据值和增量事务的完整性。 使用系统级格式收集和显示缓存内存信息。
-
公开(公告)号：US07296134B2
公开(公告)日：2007-11-13
申请号：US10777570
申请日：2004-02-11
CPC分类号： G06F12/04
摘要： A microprocessor system includes an address generator, an address selector, and memory system having multiple memory towers, which can be independently addressed. The address generator simultaneously generates a first memory address and a second memory address that is 1 row greater than the first memory address. The address selector determines whether the row portion of the first memory address or the second memory address is used for each memory tower. Because each tower can be addressed independently, a single memory access can be used to access data spanning multiple rows of the memory system.
摘要翻译： 微处理器系统包括地址发生器，地址选择器和具有多个存储器塔的存储器系统，其可以被独立地寻址。 地址产生器同时产生比第一存储器地址大1行的第一存储器地址和第二存储器地址。 地址选择器确定第一存储器地址的行部分或第二存储器地址是否用于每个存储器塔。 因为每个塔都可以独立寻址，所以可以使用单个存储器访问来访问跨越多行存储器系统的数据。
-
公开(公告)号：US08356212B2
公开(公告)日：2013-01-15
申请号：US13151661
申请日：2011-06-02
申请人： Klaus J. Oberlaender
发明人： Klaus J. Oberlaender
IPC分类号： G06F11/00
CPC分类号： G11C29/52 , G11C11/41 , G11C29/44 , G11C29/4401 , G11C2029/0409
摘要： A memory chip having a memory with a plurality of non-redundant memory lines and a plurality of redundant memory lines, and a controller configured to allocate dynamically a redundant memory line to a failed memory line during runtime.
摘要翻译： 一种具有存储器的存储器芯片，具有多个非冗余存储器线路和多个冗余存储器线路，以及控制器，被配置为在运行时间期间将冗余存储器线路分配给故障存储器线路。
-
公开(公告)号：US08078790B1
公开(公告)日：2011-12-13
申请号：US12110931
申请日：2008-04-28
申请人： Klaus J. Oberlaender
发明人： Klaus J. Oberlaender
CPC分类号： G06F12/0886 , G06F1/32 , G06F12/0846 , G06F2212/1028 , Y02D10/13
摘要： A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple cache lines. Because each tower can be addressed independently and the cache lines are split among the towers, unaligned cache access can be performed. Furthermore, power can be conserved because not all the memory towers of the cache unit needs to be activated during some memory access operations.
摘要翻译： 一个高速缓存单元多个内存塔，可独立寻址。 高速缓存行分为多个塔。 此外，存储塔的物理线路由多条高速缓存行共享。 因为可以独立地寻址每个塔，并且高速缓存行在塔之间分割，所以可以执行未对齐的高速缓存访问。 此外，可以节省功率，因为在某些存储器访问操作期间不需要激活高速缓存单元的所有存储塔。
-
-
-
-
-
-
-
-
-
搜索结果
10 条记录 (耗时 0.019 秒)
