公开(公告)号：US4448800A

公开(公告)日：1984-05-15

申请号：US403531

申请日：1982-07-30

申请人： Kohei Ehara ,  Susumu Muramoto ,  Takashi Morimoto ,  Seitaro Matsuo ,  Manabu Itsumi

发明人： Kohei Ehara ,  Susumu Muramoto ,  Takashi Morimoto ,  Seitaro Matsuo ,  Manabu Itsumi

IPC分类号： H01L21/033 ,  H01L21/768 ,  H01L21/302

CPC分类号： H01L21/7688 ,  H01L21/033 ,  Y10S148/10 ,  Y10S148/105 ,  Y10S438/951

摘要： A semiconductor manufacturing method which uses a refractory metal as a lift-off material and employs, in combination, a dry etching process suitable for forming a miniature pattern without undercutting and a film deposition method for deposing the lift-off material with directionality in a direction perpendicular to the substrate surface. A semiconductor device is fabricated by a lift-off method which is free from the fear of contamination, permits easy lift off of the lift-off material, even if large in area, and hence suitable for the formation of a high-density pattern.

摘要翻译： 一种半导体制造方法，其使用难熔金属作为剥离材料，并用组合使用适于形成无底切的微型图案的干式蚀刻工艺，以及用于沿方向取向剥离材料的膜沉积方法 垂直于衬底表面。 半导体器件通过剥离方法制造，其不受污染的恐惧，即使面积大，容易剥离剥离材料，因此适合于形成高密度图案。

公开(公告)号：US4566940A

公开(公告)日：1986-01-28

申请号：US661700

申请日：1984-10-17

申请人： Manabu Itsumi ,  Kohei Ehara ,  Susumu Muramoto ,  Seitaro Matsuo

发明人： Manabu Itsumi ,  Kohei Ehara ,  Susumu Muramoto ,  Seitaro Matsuo

IPC分类号： H01L21/3205 ,  H01L21/027 ,  H01L21/762 ,  H01L21/768 ,  H01L21/306 ,  B44C1/22 ,  C03C15/00 ,  C23F1/02

CPC分类号： H01L21/7688 ,  H01L21/0272 ,  H01L21/762 ,  Y10S438/951

摘要： A semiconductor integrated circuit in which layers such as an field isolation region, a gate electrode, interlayer insulating films and interconnection lines are formed by the combined use of a lift-off process and an ECR plasma deposition process. According to the present invention, even if vertical dimensions of patterns of the respective layers are large as compared with their lateral dimensions, the upper surfaces of the respective layers can be planarized, permitting the fabrication of an LSI of high packing density, high operating speed and high reliability which is free from shorting and breakage of the interconnection lines.

公开(公告)号：US4564997A

公开(公告)日：1986-01-21

申请号：US369235

申请日：1982-04-16

申请人： Seitaro Matsuo ,  Susumu Muramoto ,  Kohei Ehara ,  Manabu Itsumi

发明人： Seitaro Matsuo ,  Susumu Muramoto ,  Kohei Ehara ,  Manabu Itsumi

IPC分类号： H01L21/027 ,  H01L21/762 ,  H01L21/768 ,  H01L21/76 ,  H01L21/302

CPC分类号： H01L21/0272 ,  H01L21/76224 ,  H01L21/7688 ,  Y10S148/05 ,  Y10S148/131 ,  Y10S438/951 ,  Y10S438/963

摘要： A semiconductor device in which a film of an insulator a conductor is closely deposited in a groove formed in a semiconductor substrate or an insulating or conductor layer thereon to planarize the surface thereof.A semiconductor device manufacturing process in which a specimen is selectively etched away through using a resist pattern as a mask, a pattern forming film is deposited by a plasma deposition technique on the specimen, and the resist film is removed, whereby the pattern forming film closed fills up a groove formed by etching to provide a planarized surface.

摘要翻译： 一种半导体器件，其中导体的绝缘体的膜被紧密地沉积在形成在半导体衬底或其绝缘或导体层中的沟槽中以使其表面平坦化。 通过使用抗蚀剂图案作为掩模来选择性地蚀刻出样本的半导体器件制造工艺，通过等离子体沉积技术将图案形成膜沉积在样品上，并且去除抗蚀剂膜，由此图案形成膜封闭 填充通过蚀刻形成的凹槽以提供平坦化表面。

公开(公告)号：US4543592A

公开(公告)日：1985-09-24

申请号：US670661

申请日：1984-11-09

申请人： Manabu Itsumi ,  Kohei Ehara ,  Susumu Muramoto ,  Seitaro Matsuo

发明人： Manabu Itsumi ,  Kohei Ehara ,  Susumu Muramoto ,  Seitaro Matsuo

IPC分类号： H01L21/3205 ,  H01L21/027 ,  H01L21/762 ,  H01L21/768 ,  H01L27/02 ,  H01L29/06

CPC分类号： H01L21/7688 ,  H01L21/0272 ,  H01L21/762 ,  Y10S438/951

摘要： A semiconductor integrated circuit in which layers such as an field isolation region, a gate electrode, interlayer insulating films and interconnection lines are formed by the combined use of a lift-off process and an ECR plasma deposition process. According to the present invention, even if vertical dimensions of patterns of the respective layers are large as compared with their lateral dimensions, the upper surfaces of the respective layers can be planarized, permitting the fabrication of an LSI of high packing density, high operating speed and high reliability which is free from shorting and breakage of the interconnection lines.

摘要翻译： 通过组合使用剥离工艺和ECR等离子体沉积工艺形成其中诸如场隔离区域，栅电极，层间绝缘膜和互连线之类的层的半导体集成电路。 根据本发明，即使各层的图案的垂直尺寸与横向尺寸相比较大，也可以使各层的上表面平坦化，能够制造高封装浓度的LSI，高工作速度 高可靠性，无互连线短路和断线。