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    SELECTIVE DEPOSITION OF SILICON OXIDE FILMS
    7.
    发明申请
    SELECTIVE DEPOSITION OF SILICON OXIDE FILMS 审中-公开
    硅氧烷膜的选择性沉积

    公开(公告)号：US20170004974A1

    公开(公告)日：2017-01-05

    申请号：US15185282

    申请日：2016-06-17

    申请人： Applied Materials, Inc.

    发明人： Pramit MANNA ,  Abhijit Basu MALLICK

    IPC分类号： H01L21/3105 ,  H01L21/311 ,  H01L21/02

    CPC分类号： H01L21/02164 ,  C23C16/02 ,  C23C16/045 ,  C23C16/401 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02312 ,  H01L21/02315 ,  H01L21/033 ,  H01L21/0337 ,  H01L21/3213 ,  H01L21/76281 ,  H01L21/76283

    摘要： Embodiments described herein generally provide a method for filling features formed on a substrate. In one embodiment, a method for selectively forming a silicon oxide layer on a substrate is provided. The method includes selectively depositing a silicon oxide layer within a patterned feature formed on a surface of a substrate, wherein the patterned feature comprises one or more sidewalls and a deposition surface at a bottom of the patterned feature, the one or more sidewalls comprise a silicon oxide, a silicon nitride, or a combination thereof, the deposition surface essentially consists of silicon, and the selectively deposited silicon oxide layer is formed on the deposition surface by flowing tetraethyl orthosilicate (TEOS) and ozone over the patterned feature.

    摘要翻译： 本文描述的实施例通常提供用于填充形成在基底上的特征的方法。 在一个实施例中，提供了在衬底上选择性地形成氧化硅层的方法。 该方法包括在形成在衬底的表面上的图案化特征中选择性地沉积氧化硅层，其中图案化特征包括在图案化特征的底部的一个或多个侧壁和沉积表面，所述一个或多个侧壁包括硅 氧化物，氮化硅或其组合，沉积表面基本上由硅组成，并且通过在图案化特征上流动原硅酸四乙酯（TEOS）和臭氧，在沉积表面上形成选择性沉积的氧化硅层。

    Method for forming a resist under layer film and patterning process
    9.
    发明授权
    Method for forming a resist under layer film and patterning process 有权
    用于形成抗蚀剂下层膜的方法和图案化工艺

    公开(公告)号：US09230827B2

    公开(公告)日：2016-01-05

    申请号：US14253497

    申请日：2014-04-15

    申请人： SHIN-ETSU CHEMICAL CO., LTD.

    发明人： Shiori Nonaka ,  Seiichiro Tachibana ,  Daisuke Kori ,  Toshihiko Fujii ,  Tsutomu Ogihara

    IPC分类号： G03F7/11 ,  H01L21/3213 ,  G03F7/16 ,  H01L21/027 ,  H01L21/04 ,  G03F7/09 ,  H01L21/033

    CPC分类号： H01L21/32139 ,  G03F7/094 ,  G03F7/11 ,  G03F7/16 ,  G03F7/168 ,  H01L21/0274 ,  H01L21/033 ,  H01L21/042

    摘要： The present invention provides a method for forming a resist under layer film used in a lithography process, comprising: a process for applying a composition for forming a resist under layer film containing an organic compound having an aromatic unit on a substrate; and a process for heat-treating the resist under layer film applied in an atmosphere whose oxygen concentration is 10% or more at 150° C. to 600° C. for 10 to 600 seconds after heat-treating the same in an atmosphere whose oxygen concentration is less than 10% at 50 to 350° C. There can be provided a method for forming a resist under layer film having excellent filling/flattening properties so that unevenness on a substrate can be flattened even in complex processes such as multi-layer resist method and double patterning.

    摘要翻译： 本发明提供一种用于形成在光刻工艺中使用的抗蚀剂下层膜的方法，包括：在基材上涂覆含有具有芳族单元的有机化合物的抗蚀剂下层膜的组合物的方法; 以及在氧气浓度为10％以上的气氛中，在氧气浓度为10％以上的氧气中进行热处理10〜600秒的热处理后的氧化膜 在50〜350℃下浓度小于10％。可以提供一种形成具有优异的填充/压平性能的抗蚀剂下层膜的方法，使得即使在复杂的工艺中也可以使基板上的不均匀性平坦化，例如多层 抗蚀剂法和双重图案化。

    STITCH-DERIVED VIA STRUCTURES AND METHODS OF GENERATING THE SAME
    10.
    发明申请
    STITCH-DERIVED VIA STRUCTURES AND METHODS OF GENERATING THE SAME 有权
    通过结构衍生出来的结构和产生它的方法

    公开(公告)号：US20150339422A1

    公开(公告)日：2015-11-26

    申请号：US14285719

    申请日：2014-05-23

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Stephen E. Greco ,  Vincent J. McGahay ,  Rasit O. Topaloglu

    IPC分类号： G06F17/50 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768

    CPC分类号： G06F17/5068 ,  G06F17/50 ,  H01L21/033 ,  H01L21/0332 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Via-level design shapes are mapped into stitch regions of line-level design shapes design in an overlying conductive line level. A via-catching design shape is provided in an underlying conductive line level for each stitch region that does not correspond to a via-level design shape. The shapes of the stitch regions and the via-catch design shapes can be adjusted to comply with design rule constraints. Further, stitches can be optionally moved into a neighboring line-level design shape to resolve design rule conflicts. The modified design layout can eliminate via-level design shapes once all via-level design shapes are replaced with a corresponding stitch region, thereby eliminating the need to provide a via level lithographic mask. A metal interconnect structure embodying the modified design layout can be formed by employing a set of hard mask layers and without employing a lithographic mask for a via level.

    摘要翻译： 通过级别的设计形状被映射到上层导线级别的线级设计形状设计的针脚区域。 对于不对应于通孔级设计形状的每个针脚区域，在底层导电线路层中提供通孔捕捉设计形状。 可以调整针迹区域和通孔捕捉设计形状的形状以符合设计规则约束。 此外，针迹可以可选地移动到相邻的线级设计形状中以解决设计规则冲突。 一旦所有通孔级设计形状被相应的针脚区域替换，修改后的设计布局可以消除通孔级设计形状，从而不需要提供通孔级光刻掩模。 体现修改后的设计布局的金属互连结构可以通过采用一组硬掩模层而不使用用于通孔级的光刻掩模来形成。