公开(公告)号：US4746824A

公开(公告)日：1988-05-24

申请号：US921272

申请日：1986-10-21

申请人： Koichi Magome ,  Hiroyuki Koinuma ,  Haruki Toda

发明人： Koichi Magome ,  Hiroyuki Koinuma ,  Haruki Toda

IPC分类号： H03K19/094 ,  G11C5/14 ,  H03K5/02 ,  H03K17/06 ,  H03K17/687 ,  H03K19/003 ,  H03K19/096 ,  H03K5/13 ,  G11C27/02

CPC分类号： H03K19/096 ,  H03K19/00315

摘要： This invention provides a high potential hold circuit comprising: a high potential node; a high potential hold enhancement mode MOS transistor for holding a potential of the high potential node by setting the high potential hold transistor in an non-conducting state after the node is charged, having one end connected to a first input signal and the other end connected to the high potential node; a discharge enhancement mode MOS transistor for discharging the potential of the high potential node, having one end connected to the ground potential, the other end connected to the high potential node and a gate connected to a second input signal; a field relaxation enhancement mode MOS transistor located between the high potential node and the high potential hold transistor; and charge-discharge means for charging and discharging a potential of a gate of the field relaxation transistor.

摘要翻译： 本发明提供一种高电位保持电路，包括：高电位节点; 高电位保持增强模式MOS晶体管，用于通过在节点充电之后将高电位保持晶体管设置为不导通状态来保持高电位节点的电位，其一端连接到第一输入信号，另一端连接 到高电位节点; 放电增强模式MOS晶体管，用于对高电位节点的电位进行放电，其一端连接到地电位，另一端连接到高电位节点，栅极连接到第二输入信号; 位于高电位节点和高电位保持晶体管之间的场弛豫增强模式MOS晶体管; 以及用于对场弛豫晶体管的栅极的电位进行充电和放电的充放电装置。

公开(公告)号：US4678934A

公开(公告)日：1987-07-07

申请号：US884629

申请日：1986-07-11

申请人： Koichi Magome ,  Haruki Toda ,  Hiroyuki Koinuma ,  Hiroshi Sahara ,  Kiminobu Suzuki ,  Shigeo Ohshima ,  Kenji Komatsu

发明人： Koichi Magome ,  Haruki Toda ,  Hiroyuki Koinuma ,  Hiroshi Sahara ,  Kiminobu Suzuki ,  Shigeo Ohshima ,  Kenji Komatsu

IPC分类号： G11C11/40 ,  G11C8/06 ,  H03K3/356 ,  H03K3/26 ,  G11C7/00 ,  H03K17/687 ,  H03K19/094

CPC分类号： H03K3/356026 ,  G11C8/06

摘要： A flip-flop circuit has a power terminal set at 5 V, first and second output terminals, a latch section for charging one of the first and second terminals to 5 V and discharging the other one of the first and second terminals to 0 V in accordance with an input signal, a first MOS transistor having a current path connected between the power and first output terminals, a second MOS transistor for charging the gate of the first MOS transistor while the potential of the second output terminal is changed from 5 V to 0 V, and a capacitor for bootstrapping the gate potential of the first MOS transistor to turn on the first MOS transistor. The flip-flop circuit further includes a third MOS transistor, having a current path connected between the gate of the first MOS transistor and the first output terminal and a gate connected to the first output terminal, for charging the gate of the first MOS transistor when the gate potential of the first MOS transistor is dropped a predetermined level in comparison with that of the first output terminal.

摘要翻译： 触发器电路具有设置在5V的电源端子，第一和第二输出端子，用于将第一和第二端子中的一个充电至5V并将第一和第二端子中的另一个放电至0V的锁存部分 根据输入信号，具有连接在电源和第一输出端子之间的电流路径的第一MOS晶体管，第二MOS晶体管，用于对第一MOS晶体管的栅极充电，同时第二输出端子的电位从5V变为 0V，以及用于自举第一MOS晶体管的栅极电位以使第一MOS晶体管导通的电容器。 触发器电路还包括第三MOS晶体管，其具有连接在第一MOS晶体管的栅极和第一输出端子之间的电流路径和连接到第一输出端子的栅极，用于对第一MOS晶体管的栅极充电， 与第一输出端子相比，第一MOS晶体管的栅极电位下降到预定水平。

公开(公告)号：US5075887A

公开(公告)日：1991-12-24

申请号：US647202

申请日：1991-01-28

申请人： Koichi Magome ,  Masakazu Kiryu ,  Shigeo Ohshima ,  Haruki Toda ,  Hiroshi Sahara

发明人： Koichi Magome ,  Masakazu Kiryu ,  Shigeo Ohshima ,  Haruki Toda ,  Hiroshi Sahara

IPC分类号： G11C7/00 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/409

CPC分类号： G11C7/20 ,  G11C11/4072 ,  G11C11/409 ,  G11C7/00

摘要： A semiconductor memory device is disclosed which comprises, as shown in FIG. 1, a pair of column lines, memory cells connected to the corresponding column lines, a sense amplifier connected to the column lines, row lines for selecting the memory cells in accordance with a row address signal, and first and second transistors having their current paths connected between the column lines and a fixed potential supply terminal supplied with a positive power source potential or a ground potential, wherein the gates of the first and second transistors are connected to the first and second row lines for a data rewrite operation which can be selected independently of the row line.

公开(公告)号：US5319603A

公开(公告)日：1994-06-07

申请号：US778154

申请日：1991-12-24

申请人： Nobuo Watanabe ,  Koichi Magome ,  Katsumi Abe ,  Haruki Toda

发明人： Nobuo Watanabe ,  Koichi Magome ,  Katsumi Abe ,  Haruki Toda

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1075 ,  G11C2207/107

摘要： A multiport semiconductor memory device of this invention is constructed as having: a RAM having a first RAM unit and a second RAM unit; a SAM having a first SAM unit and a second SAM unit; and transfer circuit capable of selectively taking one of a split transfer state and a cross transfer state, in the split transfer state the first RAM unit and the first SAM unit being connected together and the second RAM unit and the second SAM unit being connected together, and in the cross transfer state the first RAM unit and the second SAM unit being connected together and the second RAM unit and the first SAM unit being connected together.

摘要翻译： PCT No.PCT / JP91 / 00587第 371 1991年12月24日第 102（e）日期1991年12月24日PCT 1991年4月30日PCT PCT。 公开号WO91 / 17544 日本1991年11月14日。本发明的多端口半导体存储器件被构造为具有：具有第一RAM单元和第二RAM单元的RAM; 具有第一SAM单元和第二SAM单元的SAM; 以及转移电路，其能够选择性地采取分割转印状态和交叉转印状态之一，在分离转印状态下，第一RAM单元和第一SAM单元连接在一起，并且第二RAM单元和第二SAM单元连接在一起， 并且在交叉传送状态下，第一RAM单元和第二SAM单元连接在一起，并且第二RAM单元和第一SAM单元连接在一起。

公开(公告)号：US5168468A

公开(公告)日：1992-12-01

申请号：US789036

申请日：1991-11-07

申请人： Koichi Magome ,  Hiroshi Sahara ,  Haruki Toda

发明人： Koichi Magome ,  Hiroshi Sahara ,  Haruki Toda

IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C11/418 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/818

摘要： A semiconductor memory device comprises a memory cell array, a redundant memory cell array, bit line pairs, spare bit line pairs, a column address information storage circuit having stored therein information of a column address of a faulty cell and a column address of a spare cell, column decoders, a first column selecting gate for connecting one of the bit line pairs and first data output line pairs, a second column selecting gate for connecting one of the bit line pairs and a second data output line pair, a spare column decoder for selecting a third or a fourth column selecting line, a third column selecting gate for connecting the spare bit line pairs and the first data output line pairs, a fourth column selecting gate for connecting the spare bit line pairs and the second data output line pair, a first buffer for selecting two data and amplifying and outputting, a second buffer for amplifying and outputting data from the second data output line pair, and a register for storing therein data from the first and/or second buffers.

摘要翻译： 半导体存储器件包括存储单元阵列，冗余存储单元阵列，位线对，备用位线对，列存储有故障单元的列地址的信息和备用列列地址的列地址信息存储电路 单元，列解码器，用于连接位线对和第一数据输出线对中的一个的第一列选择栅极，用于连接位线对之一和第二数据输出线对的第二列选择栅极，备用列解码器 用于选择第三或第四列选择线，用于连接备用位线对和第一数据输出线对的第三列选择栅极，用于连接备用位线对和第二数据输出线对的第四列选择栅极 用于选择两个数据并放大和输出的第一缓冲器，用于放大和输出来自第二数据输出线对的数据的第二缓冲器，以及用于存储 控制来自第一和/或第二缓冲器的数据。

公开(公告)号：US5497352A

公开(公告)日：1996-03-05

申请号：US371604

申请日：1995-01-12

申请人： Koichi Magome

发明人： Koichi Magome

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/34 ,  G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  H04N7/26 ,  H04N7/50 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1006 ,  H04N19/423 ,  H04N19/61

摘要： An improvement of a semiconductor memory device capable of designating a block write mode in which writing is effected simultaneously to a plurality of memory cells unitized by predetermined numbers and connected respectively to a plurality of column lines. Data lines correspond to a predetermined number of memory cells. The data lines and the column lines are selectively connected to each other by switches. During a block write mode, a predetermined number of column lines are simultaneously connected to the data lines corresponding thereto. During the other mode, a control unit controls the switches to connect some of the predetermined number of column liens to the data lines corresponding thereto. During the mode other than the block write mode, only a part of the predetermined number column lines are connected to the data lines, thereby reducing electric power consumption.

摘要翻译： 一种能够指定块写入模式的半导体存储器件的改进，其中写入同时进行到由预定数量组合并分别连接到多条列线的多个存储器单元。 数据线对应于预定数量的存储单元。 数据线和列线通过开关彼此选择性地连接。 在块写入模式期间，预定数量的列线同时连接到与其对应的数据线。 在其他模式期间，控制单元控制开关将预定数量的列留置数据中的一些连接到与其对应的数据线。 在块写入模式之外的模式中，只有一部分预定数量的列线连接到数据线，从而降低了电力消耗。

公开(公告)号：US08488391B2

公开(公告)日：2013-07-16

申请号：US13080261

申请日：2011-04-05

申请人： Hikaru Mochizuki ,  Yasuaki Niino ,  Koichi Magome

发明人： Hikaru Mochizuki ,  Yasuaki Niino ,  Koichi Magome

IPC分类号： G11C7/10

CPC分类号： G11C16/32 ,  G11C5/02 ,  G11C16/0483 ,  G11C16/08

摘要： A memory chip includes: a memory region; a chip determining unit configured to perform a chip determination, in writing operation, to determine whether or not the memory region is a writing target on the basis of an inputted address of writing destination, and to output a determination result of the chip determination; an address-cycle identifying unit configured to detect a final cycle of the address of writing destination, and to output a detection result at a timing before the output of the determination result; and a buffer controller configured to switch an input buffer from one state to another on the basis of the determination result, wherein the buffer controller keeps the input buffer in an active state irrespective of the determination result of the chip determination while the address-cycle identifying unit is outputting the detection result.

摘要翻译： 存储芯片包括：存储区域; 芯片确定单元，被配置为在写入操作中执行芯片确定，以基于输入的写入目的地的地址来确定存储器区域是否是写入目标，并输出芯片确定的确定结果; 地址周期识别单元，被配置为检测写入目的地地址的最后周期，并且在确定结果的输出之前的定时输出检测结果; 以及缓冲器控制器，其被配置为基于所述确定结果将输入缓冲器从一个状态切换到另一状态，其中所述缓冲器控制器将所述输入缓冲器保持在活动状态，而与所述芯片确定的确定结果无关，而所述地址周期识别 单元正在输出检测结果。

公开(公告)号：US5566128A

公开(公告)日：1996-10-15

申请号：US388661

申请日：1995-02-14

申请人： Koichi Magome

发明人： Koichi Magome

IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/407 ,  G11C29/00 ,  G11C29/04 ,  G11C8/00

CPC分类号： G11C29/80 ,  G11C7/00 ,  G11C7/10

摘要： A memory has a first bit line pair, a second bit line pair, a third bit line pair, a first data line pair, a second data line pair, a first transistor pair connecting the first bit line pair to the first data line pair, a second transistor pair connecting the second bit line pair to the second data line pair, a third transistor pair connecting the third bit line pair to the first data line pair, a fourth transistor pair connecting the third bit line pair to the second data line pair, a first selection line connected to the first transistor pair for switching ON/OFF of the first transistor pair, a second selection line connected to the second transistor pair for switching ON/OFF of the second transistor pair, a third selection line connected to the third transistor pair for switching ON/OFF of the third transistor pair, and a fourth selection line connected to the fourth transistor pair for switching ON/OFF of the fourth transistor pair.

摘要翻译： 存储器具有第一位线对，第二位线对，第三位线对，第一数据线对，第二数据线对，将第一位线对连接到第一数据线对的第一晶体管对， 将第二位线对与第二数据线对连接的第二晶体管对，将第三位线对连接到第一数据线对的第三晶体管对，将第三位线对连接到第二数据线对的第四晶体管对 连接到第一晶体管对的第一选择线，用于切换第一晶体管对的导通/截止;连接到第二晶体管对的第二选择线，用于切换第二晶体管对的导通/截止;第三选择线，连接到第一晶体管对， 用于切换第三晶体管对的导通/截止的第三晶体管对，以及连接到第四晶体管对的第四选择线，用于切换第四晶体管对的导通/截止。