公开(公告)号：US20120314510A1

公开(公告)日：2012-12-13

申请号：US13471360

申请日：2012-05-14

Applicant: Hidetoshi IKEDA ,  Koichi TAKEDA

Inventor： Hidetoshi IKEDA ,  Koichi TAKEDA

IPC: G11C7/06 ,  G11C7/08

CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1048 ,  G11C11/419

Abstract: Provided is a semiconductor memory device including a plurality of memory cells arranged in a matrix, a plurality of word lines arranged corresponding to each row of the memory cells, a plurality of bit line pairs arranged corresponding to each column of the memory cells, a column selector that selects any of the plurality of bit line pairs based on a column selection signal and connects the selected bit line pair to a data line pair, a precharge circuit that precharges the data line pair, a sense amplifier that amplifies a potential difference of the data line pair, and a control circuit that controls current for driving the sense amplifier based on potentials of the data line pair after a lapse of a specified period from start of amplification of the potential difference of the precharged data line pair by the sense amplifier.

Abstract translation: 提供了一种半导体存储器件，其包括以矩阵形式布置的多个存储器单元，对应于存储器单元的每一行布置的多个字线，对应于存储器单元的每列布置的多个位线对，列 选择器，其基于列选择信号选择多个位线对中的任何一个，并将所选择的位线对连接到数据线对，预充电数据线对的预充电电路，放大电位差的读出放大器 数据线对以及控制电路，其控制电流，用于在由读出放大器从预充电数据线对的电位差的放大开始经过指定时段之后基于数据线对的电位驱动读出放大器。

公开(公告)号：US20120202330A1

公开(公告)日：2012-08-09

申请号：US13367884

申请日：2012-02-07

Applicant: Koichi TAKEDA ,  Kiyoshi TAKEUCHI

Inventor： Koichi TAKEDA ,  Kiyoshi TAKEUCHI

IPC: H01L21/336

CPC classification number: H01L21/845 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1211 ,  Y10S257/903

Abstract: The present invention provides a semiconductor device including SRAM cell units each including a data holding section made up of a pair of driving transistors and a pair of load transistors, a data write section made up of a pair of access transistors, and a data read section made up of an access transistor and a driving transistor, wherein each of the transistors includes a semiconductor layer projecting upward from a base plane, a gate electrode extending from a top to opposite side surfaces of the semiconductor layer so as to stride the semiconductor layer, a gate insulating film between the gate electrode and the semiconductor layer, and source/drain areas, a longitudinal direction of each of the semiconductor layers is provided along a first direction, and for all the corresponding transistors between the SRAM cell units adjacent to each other in the first direction, the semiconductor layer in one of the corresponding transistors is located on a center line of the semiconductor layer along the first direction in the other transistor.

Abstract translation: 本发明提供了包括SRAM单元单元的半导体器件，每个SRAM单元包括由一对驱动晶体管和一对负载晶体管构成的数据保持部分，由一对存取晶体管构成的数据写入部分和数据读取部分 由存取晶体管和驱动晶体管构成，其中每个晶体管包括从基板向上突出的半导体层，从半导体层的顶部延伸到相对侧表面的栅电极，以跨越半导体层， 栅极电极和半导体层之间的栅极绝缘膜以及源极/漏极区域，沿着第一方向设置每个半导体层的纵向方向，并且对于彼此相邻的SRAM单元单元之间的所有对应的晶体管 在第一方向上，一个对应的晶体管中的半导体层位于半导体1a的中心线上 沿另一个晶体管的第一个方向。

公开(公告)号：US20110222360A1

公开(公告)日：2011-09-15

申请号：US13041566

申请日：2011-03-07

Applicant: Koichi TAKEDA

Inventor： Koichi TAKEDA

IPC: G11C7/00

CPC classification number: G11C7/02 ,  G11C5/14 ,  G11C11/413

Abstract: A semiconductor storage device in accordance with the present invention includes a first SRAM cell that stores data, and a word line circuit that outputs a first control signal used to activate the first SRAM cell. The word line control circuit gradually raises the voltage level of the first control signal from a substrate potential to a first power supply potential in a first activation period, maintains the voltage level of the first control signal at the first power supply potential in a second activation period subsequent to the first activation period, and raises the voltage level of the first control signal from the first power supply potential to a second power supply potential in a third activation period subsequent to the second activation period.

Abstract translation: 根据本发明的半导体存储装置包括存储数据的第一SRAM单元和输出用于激活第一SRAM单元的第一控制信号的字线电路。 字线控制电路在第一激活期间逐渐地将第一控制信号的电压电平从衬底电位升高到第一电源电位，在第二激活期间将第一控制信号的电压电平维持在第一电源电位 并且在第二激活周期之后的第三激活周期中将第一控制信号的电压电平从第一电源电位升高到第二电源电位。

公开(公告)号：US20090172415A1

公开(公告)日：2009-07-02

申请号：US12331587

申请日：2008-12-10

Applicant: Koichi TAKEDA

Inventor： Koichi TAKEDA

IPC: G06F12/14

CPC classification number: G06F12/1408

Abstract: The control unit includes a CPU which generates an access signal for performing writing or reading on the external memory, encryption/decryption means which, when the access signal is used for writing, encrypts an address designated by the CPU to generate a write address and encrypts write data contained in the access signal to generate write encrypted data, and which, when the access signal is used for reading, encrypts an address designated by the CPU to generate a read address and decrypts the encrypted data read from the external memory to generate plaintext data, and external control means which writes the write encrypted data in a position designated by the write address generated by the encryption/decryption means and which reads the encrypted data from a position designated by the read address generated by the encryption/decryption means and supplies the same to the encryption/decryption means for its decryption.

Abstract translation: 控制单元包括生成用于在外部存储器上进行写入或读取的访问信号的CPU，加密/解密装置，当访问信号用于写入时，加密由CPU指定的地址以产生写入地址并加密 写入访问信号中包含的数据以产生写入加密数据，当访问信号用于读取时，加密由CPU指定的地址以生成读取地址并对从外部存储器读取的加密数据进行解密以产生明文 数据和外部控制装置，其将写入加密数据写入由加密/解密装置生成的写入地址指定的位置，并且从由加密/解密装置产生的读取地址指定的位置读取加密数据， 与加密/解密手段相同，用于其解密。