公开(公告)号：US20050116268A1

公开(公告)日：2005-06-02

申请号：US10997905

申请日：2004-11-29

申请人： Koichi Tahira ,  Hiroki Usui ,  Hiroshi Hasegawa ,  Makoto Aikawa

发明人： Koichi Tahira ,  Hiroki Usui ,  Hiroshi Hasegawa ,  Makoto Aikawa

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L29/423 ,  H01L21/336 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L27/0207 ,  H01L29/4238 ,  H01L29/94

摘要： A semiconductor device of the generation with the minimum processing dimensions of 90 nm, or later, wherein variation of processing dimensions of gate electrodes in a logic block and a power source noise are suppressed; wherein a gate electrode formed to have a comb-shaped pattern is formed on a normal cell region, a dummy gate electrode formed to have a comb-shaped pattern is formed on a vacant region, a wiring for applying a predetermined voltage is connected respectively to at least a part of the dummy gate and the semiconductor substrate (source drain regions), and an electrostatic capacity between the part of the dummy gate electrode and the semiconductor substrate constitutes a decoupling capacitor of the power source.

摘要翻译： 最小处理尺寸为90nm或以后的生成半导体器件，其中抑制了逻辑块中的栅电极的处理尺寸的变化和电源噪声; 其中在正常单元区域上形成具有梳状图案的栅电极，在空区域上形成具有梳形图案的伪栅电极，分别连接施加预定电压的布线 虚拟栅极和半导体衬底（源极漏极区域）的至少一部分，虚拟栅极电极和半导体衬底的部分之间的静电电容构成电源的去耦电容器。

公开(公告)号：US07456446B2

公开(公告)日：2008-11-25

申请号：US10997905

申请日：2004-11-29

申请人： Koichi Tahira ,  Hiroki Usui ,  Hiroshi Hasegawa ,  Makoto Aikawa

发明人： Koichi Tahira ,  Hiroki Usui ,  Hiroshi Hasegawa ,  Makoto Aikawa

IPC分类号： H01L27/10

CPC分类号： H01L27/0207 ,  H01L29/4238 ,  H01L29/94

摘要： A semiconductor device of the generation with the minimum processing dimensions of 90 nm, or later, wherein variation of processing dimensions of gate electrodes in a logic block and a power source noise are suppressed; wherein a gate electrode formed to have a comb-shaped pattern is formed on a normal cell region, a dummy gate electrode formed to have a comb-shaped pattern is formed on a vacant region, a wiring for applying a predetermined voltage is connected respectively to at least a part of the dummy gate and the semiconductor substrate (source drain regions), and an electrostatic capacity between the part of the dummy gate electrode and the semiconductor substrate constitutes a decoupling capacitor of the power source.

摘要翻译： 最小处理尺寸为90nm或以后的生成半导体器件，其中抑制了逻辑块中的栅电极的处理尺寸的变化和电源噪声; 其中在正常单元区域上形成具有梳状图案的栅电极，在空区域上形成具有梳形图案的伪栅电极，分别连接施加预定电压的布线 虚拟栅极和半导体衬底（源极漏极区域）的至少一部分，虚拟栅极电极和半导体衬底的部分之间的静电电容构成电源的去耦电容器。