公开(公告)号：US06711726B2

公开(公告)日：2004-03-23

申请号：US09827932

申请日：2001-04-09

申请人： Koji Hirakimoto ,  Ken Saito ,  Tatsuya Umeda

发明人： Koji Hirakimoto ,  Ken Saito ,  Tatsuya Umeda

IPC分类号： G06F1750

CPC分类号： G06F17/5068

摘要： A buffer cell and an inverter cell are embedded in advance in an internal open space of each of mega-cells and IO cells composing a semiconductor integrated circuit. Thereafter, in cases where it is expected that a cross-talk noise is generated in a signal transmitting through a particular wire of the semiconductor integrated circuit, one mega-cell or one IO cell, which is placed in a position nearest to a generation position of the cross-talk noise, is selected from the mega-cells and the IO cells, and the buffer cell or the inverter cell embedded in the selected mega-cell or the selected IO cell is inserted into the particular wire. Therefore, because the capacitance between the particular wire and each wire adjacent to the particular wire is reduced, the cross-talk noise can be reduced.

摘要翻译： 预先将缓冲单元和反相器单元嵌入构成半导体集成电路的各单元和IO单元的内部开放空间中。 此后，在期望在通过半导体集成电路的特定导线发送的信号中产生串扰噪声的情况下，放置在最靠近发电位置的位置的一个兆电池或一个IO电池 的串扰噪声是从巨型单元和IO单元中选出的，并且嵌入所选择的单元格或所选择的IO单元中的缓冲单元或反相器单元插入到特定的导线中。 因此，由于特定导线和与特定导线相邻的每根线之间的电容减小，所以可以降低串扰噪声。

公开(公告)号：US07017134B2

公开(公告)日：2006-03-21

申请号：US10836324

申请日：2004-05-03

申请人： Ken Saito ,  Yoshio Inoue ,  Koji Hirakimoto

发明人： Ken Saito ,  Yoshio Inoue ,  Koji Hirakimoto

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  H01L27/0203

摘要： An automatic floor-planning method includes extracting a register and a logic operation cell in a semiconductor integrated-circuit unit, extracting a first register set and a second register set that are assumed to input and receive a signal to and from the logic operation cell directly or via other logic operation cell, respectively, creating a set of the logic operation cells as a cluster cell, determining a layout of the cluster cell and the register, selecting a logic level block for which a floor plan is performed, and determining an arrangement and wiring area such that the arrangement and wiring area of the logic level block includes as many cells as possible that belong to the logic level block.

摘要翻译： 自动楼层规划方法包括提取半导体集成电路单元中的寄存器和逻辑运算单元，提取假设为直接从逻辑运算单元输入和接收信号的第一寄存器组和第二寄存器组 或经由其他逻辑运算单元，创建一组逻辑运算单元作为集群单元，确定集群单元和寄存器的布局，选择执行平面图的逻辑电平块，以及确定布置 和布线区域，使得逻辑电平块的布置和布线区域包括属于逻辑电平块的尽可能多的单元。

公开(公告)号：US06938232B2

公开(公告)日：2005-08-30

申请号：US10320635

申请日：2002-12-17

申请人： Ken Saito ,  Yoshio Inoue ,  Kazuhiro Takahashi ,  Koji Hirakimoto

发明人： Ken Saito ,  Yoshio Inoue ,  Kazuhiro Takahashi ,  Koji Hirakimoto

IPC分类号： G06F17/50 ,  H01L21/82

CPC分类号： G06F17/5072

摘要： A floorplanning apparatus includes a seed position decision section for deciding a placement position of a logic seed of each hierarchical block; a cell placement section for placing cells belonging to the hierarchical block around the placement position of each logic seed; and a placement region decision section for deciding placement and routing regions of each hierarchical block considering cell placement results produced by the cell placement section.

摘要翻译： 布局规划设备包括种子位置决定部分，用于确定每个分级块的逻辑种子的放置位置; 单元放置部，用于将属于分层块的单元放置在每个逻辑种子的放置位置周围; 以及放置区域判定部，其考虑由所述单元放置部生成的单元布置结果，决定各分层块的布局和布线区域。

公开(公告)号：US08966596B2

公开(公告)日：2015-02-24

申请号：US13615296

申请日：2012-09-13

申请人： Ken Saito

发明人： Ken Saito

IPC分类号： H04L29/06

CPC分类号： G06F21/608

摘要： A communication apparatus is configured to communicate with a service providing server. The service providing server provides a data upload service and, for each user, associate and stores authentication information for a user and an e-mail address for the user. The communication apparatus includes: a storage control unit storing specific authentication information for a specific user in a memory; an acquisition unit which, when an upload instruction for uploading target data to the service providing server is input from the specific user, uses the specific authentication information in the memory to acquire a specific e-mail address, which is stored in association with the specific authentication information, from the service providing server; and an upload unit that transmits a specific e-mail including the target data and the specific e-mail address as a transmission destination address, for uploading the target data to the service providing server.

摘要翻译： 通信装置被配置为与服务提供服务器进行通信。 服务提供服务器提供数据上传服务，并且对于每个用户，关联并存储用户的认证信息和用户的电子邮件地址。 通信装置包括：存储控制单元，用于存储特定用户在存储器中的特定认证信息; 当从特定用户输入用于将目标数据上传到服务提供服务器的上传指令时，采用该存储器中的特定认证信息来获取特定的电子邮件地址，该特定电子邮件地址与特定的 来自服务提供服务器的认证信息; 以及上传单元，其将包括目标数据和特定电子邮件地址的特定电子邮件发送为发送目的地地址，以将目标数据上传到服务提供服务器。

公开(公告)号：US08621415B2

公开(公告)日：2013-12-31

申请号：US13372434

申请日：2012-02-13

申请人： Kenta Suto ,  Satoshi Shibatani ,  Ryoji Ishikawa ,  Ken Saito ,  Yoshio Inoue

发明人： Kenta Suto ,  Satoshi Shibatani ,  Ryoji Ishikawa ,  Ken Saito ,  Yoshio Inoue

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/5068 ,  G06F2217/78 ,  G06F2217/84

摘要： A power domain is automatically generated.A computer performs a function simulation process 9 for evaluating whether or not a designed circuit satisfies a specification, and a clustering process 10 which obtains a power domain by clustering logical blocks in which activation timings are within a range, based on the result of the function simulation process. Since the power domain is obtained by a process performed by the computer, the power domain can be optimized compared to a case when it is obtained by hand (manual work of the designer).

摘要翻译： 电源域自动生成。 计算机执行功能模拟处理9，用于评估设计的电路是否满足规格;以及聚类处理10，其基于功能的结果，通过对激活定时在一定范围内的逻辑块进行聚类而获得功率域 模拟过程。 由于通过计算机执行的处理获得功率域，所以与通过手动（设计人员的手工工作）获得的情况相比，能够优化功率域。

公开(公告)号：US08108809B2

公开(公告)日：2012-01-31

申请号：US12219371

申请日：2008-07-21

申请人： Toshiyuki Sadakane ,  Ken Saito ,  Yoshio Inoue

发明人： Toshiyuki Sadakane ,  Ken Saito ,  Yoshio Inoue

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the integrated circuit and routes connecting the cells, and the routing analysis method comprises a step (Step 1) of obtaining the sum of areas of a plurality of cells, the number of cells or the number of routes connecting the cells from the netlist, to be defined as a constant C, and calculating a layout area S which is an area of a square layout region, by dividing the constant C by a predetermined constant U, a step (Step 2) of calculating a total route length L by multiplying a half perimeter length H of the layout region having the layout area S obtained in Step 1 by a predetermined coefficient α, and a step (Step 3) of calculating a routing difficulty index by dividing the total route length L by the layout area S. Thus, the present invention provides a routing analysis method for an integrated circuit, which, allows calculation of routing difficulty index with high accuracy of prediction.

摘要翻译： 本发明涉及一种从网表上对集成电路进行路由分析的路由分析方法，网表是构成集成电路的多个小区的信息和连接小区的路由，路由分析方法包括步骤（步骤1 ），将要定义为常数C的多个单元的区域的数量，单元的数量或将单元从网表连接的路线的数量进行计算，并计算作为正方形的面积的布局区域S 布局区域，通过将常数C除以预定的常数U，通过将具有步骤1中获得的布局区域S的布局区域的半周长H乘以预定的步骤（步骤2）来计算总路线长度L的步骤（步骤2） 系数α，以及通过将总路由长度L除以布局区域S来计算路由难度指标的步骤（步骤3）。因此，本发明提供了一种用于集成的路由分析方法 其中，允许以高精度的预测计算路由难度指数。

公开(公告)号：US20110029818A1

公开(公告)日：2011-02-03

申请号：US12727834

申请日：2010-03-19

申请人： Ken Saito

发明人： Ken Saito

IPC分类号： G06F11/07

CPC分类号： G06F11/0766 ,  G06F11/079

摘要： An information processing device may comprise a log file creating unit and a first storage controlling unit. The log file creating unit may be configured to create, each time information is input, one log file that includes log information indicating an input of the information. The storage controlling unit may be configured to store, each time the one log file is created, the one log file in a storage area.

摘要翻译： 信息处理设备可以包括日志文件创建单元和第一存储控制单元。 日志文件创建单元可以被配置为在每次输入信息时创建包括指示信息的输入的日志信息的一个日志文件。 存储控制单元可以被配置为在每次创建一个日志文件时将一个日志文件存储在存储区域中。

公开(公告)号：US20080295055A1

公开(公告)日：2008-11-27

申请号：US12219371

申请日：2008-07-21

申请人： Toshiyuki Sadakane ,  Ken Saito ,  Yoshio Inoue

发明人： Toshiyuki Sadakane ,  Ken Saito ,  Yoshio Inoue

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the integrated circuit and routes connecting the cells, and the routing analysis method comprises a step (Step 1) of obtaining the sum of areas of a plurality of cells, the number of cells or the number of routes connecting the cells from the netlist, to be defined as a constant C, and calculating a layout area S which is an area of a square layout region, by dividing the constant C by a predetermined constant U, a step (Step 2) of calculating a total route length L by multiplying a half perimeter length H of the layout region having the layout area S obtained in Step 1 by a predetermined coefficient α, and a step (Step 3) of calculating a routing difficulty index by dividing the total route length L by the layout area S. Thus, the present invention provides a routing analysis method for an integrated circuit, which, allows calculation of routing difficulty index with high accuracy of prediction.

摘要翻译： 本发明涉及一种从网表上对集成电路进行路由分析的路由分析方法，网表是构成集成电路的多个小区的信息和连接小区的路由，路由分析方法包括步骤（步骤1 ），将要定义为常数C的多个单元的区域的数量，单元的数量或将单元从网表连接的路线的数量进行计算，并计算作为正方形的面积的布局区域S 布局区域，通过将常数C除以预定的常数U，通过将具有步骤1中获得的布局区域S的布局区域的半周长H乘以预定的步骤（步骤2）来计算总路线长度L的步骤（步骤2） 系数α，以及通过将总路由长度L除以布局区域S来计算路由难度指标的步骤（步骤3）。因此，本发明提供了一种用于int的路由分析方法 集成电路，允许以高精度的预测计算路由难度指标。

公开(公告)号：US07105587B2

公开(公告)日：2006-09-12

申请号：US10278214

申请日：2002-10-21

申请人： Christopher D. Tagge ,  Jacob Freas Pollock ,  David S. Soane ,  Ken Saito ,  Lennard F. Torres

发明人： Christopher D. Tagge ,  Jacob Freas Pollock ,  David S. Soane ,  Ken Saito ,  Lennard F. Torres

IPC分类号： C08J9/00

CPC分类号： C04B28/04 ,  C04B24/163 ,  C04B24/2652 ,  C04B28/14 ,  C04B2103/0045 ,  C04B2103/0046 ,  C04B2111/00405 ,  C04B2111/0062 ,  C08J9/0066 ,  C08J9/14 ,  C08K9/08 ,  E04C2/043 ,  C04B22/068 ,  C04B22/12 ,  C04B24/243 ,  C04B24/282 ,  C04B38/00 ,  C04B2103/0067 ,  C04B24/2641

摘要： A method and composition for polymer-reinforced composite cementitious construction materials is described. In one embodiment, a crosslinking component is mixed with a high molecular weight strengthening component and an inorganic cementitious material. The addition of the mixture to water causes a crosslinked molecular network to form within the hydrated, composite cementitious construction material. Both enhanced flexural strength and improved nail-pull resistance are shown, allowing a reduction in weight of the composite cementitious construction material compared to cementitious construction materials made according to other known methods.

公开(公告)号：US07048794B2

公开(公告)日：2006-05-23

申请号：US10952122

申请日：2004-09-27

申请人： Christopher D. Tagge ,  Jacob Freas Pollock ,  Ken Saito

发明人： Christopher D. Tagge ,  Jacob Freas Pollock ,  Ken Saito

IPC分类号： C04B24/10 ,  C04B28/10 ,  C08L3/04 ,  C08L3/06 ,  C08L3/08

CPC分类号： C04B28/14 ,  C04B24/383 ,  C04B2111/0062 ,  C08L3/04 ,  C04B20/023 ,  C04B14/42

摘要： An inorganic-organic composite comprises an inorganic phase, such as gypsum crystals, and a film forming organic phase. The film forming organic phase is selected from substituted starches having a degree of polymerization; degree of substitution and viscosity such that the substituted starches are insoluble in water during mixing but dissolve at a higher processing temperature during forming, setting or drying of the composite. Thus, excessive migration of the substitute starch is prevented and the composite is substantially strengthened.

摘要翻译： 无机 - 有机复合材料包括无机相，例如石膏晶体和成膜有机相。 成膜有机相选自具有聚合度的取代淀粉; 取代度和粘度使得取代的淀粉在混合期间不溶于水，但在复合材料的成型，固化或干燥过程中在较高的加工温度下溶解。 因此，可以防止替代淀粉的过度迁移，并且复合物显着增强。