公开(公告)号：US20060157734A1

公开(公告)日：2006-07-20

申请号：US11331292

申请日：2006-01-12

申请人： Koji Onodera ,  Mitsuhiro Nakamura ,  Tomoya Nishida

发明人： Koji Onodera ,  Mitsuhiro Nakamura ,  Tomoya Nishida

IPC分类号： H01L31/0328

CPC分类号： H01L29/66462 ,  H01L29/0692 ,  H01L29/7785

摘要： A semiconductor device is provided. The semiconductor device in which a field effect transistor utilizing a heterojunction is formed in a device formation region sectioned by a device separation region of a substrate comprising a semiconductor layer laminated while including a semiconductor layer having a heterojunction on a semiconductor substrate. The device separation region is composed of a layer in which a conductive impurity is introduced, and an electrode to which a positive voltage is to be applied is formed on the device separation region, specifically on the surface of at least a part of the device separation region in the periphery of the field effect transistor.

摘要翻译： 提供半导体器件。 其中利用异质结的场效应晶体管的半导体器件形成在由包括半导体层的衬底的器件分离区域分割的器件形成区域中，该衬底包括半导体衬底上具有异质结的半导体层。 器件分离区域由引入导电杂质的层构成，在器件分离区域上形成正电压的电极，特别是在器件分离区域的至少一部分的表面上 区域在场效应晶体管的外围。

公开(公告)号：US07579634B2

公开(公告)日：2009-08-25

申请号：US11331292

申请日：2006-01-12

申请人： Koji Onodera ,  Mitsuhiro Nakamura ,  Tomoya Nishida

发明人： Koji Onodera ,  Mitsuhiro Nakamura ,  Tomoya Nishida

IPC分类号： H01L29/20

CPC分类号： H01L29/66462 ,  H01L29/0692 ,  H01L29/7785

摘要： A semiconductor device is provided. The semiconductor device in which a field effect transistor utilizing a heterojunction is formed in a device formation region sectioned by a device separation region of a substrate comprising a semiconductor layer laminated while including a semiconductor layer having a heterojunction on a semiconductor substrate. The device separation region is composed of a layer in which a conductive impurity is introduced, and an electrode to which a positive voltage is to be applied is formed on the device separation region, specifically on the surface of at least a part of the device separation region in the periphery of the field effect transistor.

摘要翻译： 提供半导体器件。 其中利用异质结的场效应晶体管的半导体器件形成在由包括半导体层的衬底的器件分离区域分割的器件形成区域中，该衬底包括半导体衬底上具有异质结的半导体层。 器件分离区域由引入导电杂质的层构成，在器件分离区域上形成正电压的电极，特别是在器件分离区域的至少一部分的表面上 区域在场效应晶体管的外围。

公开(公告)号：US20090280634A1

公开(公告)日：2009-11-12

申请号：US12505907

申请日：2009-07-20

申请人： Koji Onodera ,  Mitsuhiro Nakamura ,  Tomoya Nishida

发明人： Koji Onodera ,  Mitsuhiro Nakamura ,  Tomoya Nishida

IPC分类号： H01L21/28

CPC分类号： H01L29/66462 ,  H01L29/0692 ,  H01L29/7785

摘要： A semiconductor device is provided. The semiconductor device in which a field effect transistor utilizing a heterojunction is formed in a device formation region sectioned by a device separation region of a substrate comprising a semiconductor layer laminated while including a semiconductor layer having a heterojunction on a semiconductor substrate. The device separation region is composed of a layer in which a conductive impurity is introduced, and an electrode to which a positive voltage is to be applied is formed on the device separation region, specifically on the surface of at least a part of the device separation region in the periphery of the field effect transistor.

摘要翻译： 提供半导体器件。 其中利用异质结的场效应晶体管的半导体器件形成在由包括半导体层的衬底的器件分离区域分割的器件形成区域中，该半导体层在半导体衬底上包括具有异质结的半导体层的同时被层叠。 器件分离区域由引入导电杂质的层构成，在器件分离区域上形成正电压的电极，特别是在器件分离区域的至少一部分的表面上 区域在场效应晶体管的外围。

公开(公告)号：US07977198B2

公开(公告)日：2011-07-12

申请号：US12505907

申请日：2009-07-20

申请人： Koji Onodera ,  Mitsuhiro Nakamura ,  Tomoya Nishida

发明人： Koji Onodera ,  Mitsuhiro Nakamura ,  Tomoya Nishida

IPC分类号： H01L21/336

CPC分类号： H01L29/66462 ,  H01L29/0692 ,  H01L29/7785

摘要： A semiconductor device is provided. The semiconductor device in which a field effect transistor utilizing a heterojunction is formed in a device formation region sectioned by a device separation region of a substrate comprising a semiconductor layer laminated while including a semiconductor layer having a heterojunction on a semiconductor substrate. The device separation region is composed of a layer in which a conductive impurity is introduced, and an electrode to which a positive voltage is to be applied is formed on the device separation region, specifically on the surface of at least a part of the device separation region in the periphery of the field effect transistor.

摘要翻译： 提供半导体器件。 其中利用异质结的场效应晶体管的半导体器件形成在由包括半导体层的衬底的器件分离区域分割的器件形成区域中，该衬底包括半导体衬底上具有异质结的半导体层。 器件分离区域由引入导电杂质的层构成，在器件分离区域上形成正电压的电极，特别是在器件分离区域的至少一部分的表面上 区域在场效应晶体管的外围。

公开(公告)号：US08575658B2

公开(公告)日：2013-11-05

申请号：US13538583

申请日：2012-06-29

申请人： Shinichi Tamari ,  Mitsuhiro Nakamura ,  Koji Wakizono ,  Tomoya Nishida ,  Yuji Ibusuki

发明人： Shinichi Tamari ,  Mitsuhiro Nakamura ,  Koji Wakizono ,  Tomoya Nishida ,  Yuji Ibusuki

IPC分类号： H01L29/80

CPC分类号： H01L29/7787 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/098 ,  H01L29/205 ,  H01L29/66462

摘要： A semiconductor device includes a compound semiconductor substrate; a first conductivity type-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a first channel layer; a first conductivity type first barrier layer that forms a heterojunction with the first channel layer, and supplies a first conductivity type charge to the first channel layer; and a second conductivity type gate region that has a pn junction-type potential barrier against the first conductivity type first barrier layer; and a second conductivity type-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a second conductivity type second channel layer, and a first conductivity type gate region that has a pn junction-type potential barrier against the second conductivity type second channel layer.

摘要翻译： 半导体器件包括化合物半导体衬底; 形成在所述化合物半导体衬底上的第一导电型沟道场效应晶体管区，并且包括第一沟道层; 第一导电型第一阻挡层，与第一沟道层形成异质结，并向第一沟道层提供第一导电型电荷; 以及对所述第一导电型第一阻挡层具有pn结型势垒的第二导电型栅极区; 以及形成在所述化合物半导体衬底上并且包括第二导电类型的第二沟道层的第二导电类型沟道场效应晶体管区域和具有抵抗第二导电性的pn结型势垒的第一导电型栅极区 键入第二通道层。

公开(公告)号：US08378389B2

公开(公告)日：2013-02-19

申请号：US12805160

申请日：2010-07-15

申请人： Shinichi Tamari ,  Mitsuhiro Nakamura ,  Koji Wakizono ,  Tomoya Nishida ,  Yuji Ibusuki

发明人： Shinichi Tamari ,  Mitsuhiro Nakamura ,  Koji Wakizono ,  Tomoya Nishida ,  Yuji Ibusuki

IPC分类号： H01L29/80

CPC分类号： H01L29/7787 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/098 ,  H01L29/205 ,  H01L29/66462

摘要： A semiconductor device includes: a compound semiconductor substrate; an n-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a first channel layer; an n-type first barrier layer that forms a heterojunction with the first channel layer, and supplies an n-type charge to the first channel layer; and a p-type gate region that has a pn junction-type potential barrier against the n-type first barrier layer; and a p-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a p-type second channel layer, and an n-type gate region that has a pn junction-type potential barrier against the p-type second channel layer.

摘要翻译： 半导体器件包括：化合物半导体衬底; 形成在所述化合物半导体衬底上并且包括第一沟道层的n沟道场效应晶体管区; n型第一阻挡层，与第一沟道层形成异质结，并向第一沟道层提供n型电荷; 以及对n型第一阻挡层具有pn结型势垒的p型栅极区域; 以及形成在化合物半导体衬底上的p沟道场效应晶体管区，并且包括p型第二沟道层和对p型第二沟道pn结型势垒的n型栅极区 通道层。

公开(公告)号：US20110024798A1

公开(公告)日：2011-02-03

申请号：US12805160

申请日：2010-07-15

申请人： Shinichi Tamari ,  Mitsuhiro Nakamura ,  Koji Wakizono ,  Tomoya Nishida ,  Yuji Ibusuki

发明人： Shinichi Tamari ,  Mitsuhiro Nakamura ,  Koji Wakizono ,  Tomoya Nishida ,  Yuji Ibusuki

IPC分类号： H01L27/085 ,  H01L21/8238 ,  H01L21/335 ,  H01L29/778

CPC分类号： H01L29/7787 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/098 ,  H01L29/205 ,  H01L29/66462

摘要： A semiconductor device includes: a compound semiconductor substrate; an n-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a first channel layer; an n-type first barrier layer that forms a heterojunction with the first channel layer, and supplies an n-type charge to the first channel layer; and a p-type gate region that has a pn junction-type potential barrier against the n-type first barrier layer; and a p-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a p-type second channel layer, and an n-type gate region that has a pn junction-type potential barrier against the p-type second channel layer.

摘要翻译： 半导体器件包括：化合物半导体衬底; 形成在所述化合物半导体衬底上并且包括第一沟道层的n沟道场效应晶体管区; n型第一阻挡层，与第一沟道层形成异质结，并向第一沟道层提供n型电荷; 以及对n型第一阻挡层具有pn结型势垒的p型栅极区域; 以及形成在化合物半导体衬底上的p沟道场效应晶体管区，并且包括p型第二沟道层和对p型第二沟道pn结型势垒的n型栅极区 通道层。

公开(公告)号：US20050118818A1

公开(公告)日：2005-06-02

申请号：US10996013

申请日：2004-11-23

申请人： Tomoya Nishida

发明人： Tomoya Nishida

IPC分类号： H01L21/3063 ,  H01L21/306 ,  H01L21/335 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/095 ,  H01L21/338 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L29/66462 ,  H01L21/30612 ,  H01L21/823437 ,  H01L27/0883

摘要： In an etching method, an etching amount is controlled on the basis of the number of times an etching process is performed under the condition that an etching amount is determined independently of an etching time. Accordingly, the etching can be performed in step-by-step manner, whereby enabling the control of the etching amount at high precision.

摘要翻译： 在蚀刻方法中，在蚀刻量独立于蚀刻时间的条件下，基于蚀刻处理的次数来控制蚀刻量。 因此，可以一步一步地进行蚀刻，从而能够高精度地控制蚀刻量。

公开(公告)号：US07153710B2

公开(公告)日：2006-12-26

申请号：US10996013

申请日：2004-11-23

申请人： Tomoya Nishida

发明人： Tomoya Nishida

IPC分类号： H01L21/00

CPC分类号： H01L29/66462 ,  H01L21/30612 ,  H01L21/823437 ,  H01L27/0883

摘要： In an etching method, an etching amount is controlled on the basis of the number of times an etching process is performed under the condition that an etching amount is determined independently of an etching time. Accordingly, the etching can be performed in step-by-step manner, whereby enabling the control of the etching amount at high precision.

摘要翻译： 在蚀刻方法中，在蚀刻量独立于蚀刻时间的条件下，基于蚀刻处理的次数来控制蚀刻量。 因此，可以一步一步地进行蚀刻，从而能够高精度地控制蚀刻量。