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1.发明申请公开(公告)号：US20060114918A1
公开(公告)日：2006-06-01
申请号：US11125207
申请日：2005-05-10
申请人： Junichi Ikeda , Koji Oshikiri , Atsuhiro Oizumi , Yutaka Maita , Satoru Numakura , Noriyuki Terao , Yasuyuki Shindoh , Tohru Sasaki , Koji Takeo
发明人： Junichi Ikeda , Koji Oshikiri , Atsuhiro Oizumi , Yutaka Maita , Satoru Numakura , Noriyuki Terao , Yasuyuki Shindoh , Tohru Sasaki , Koji Takeo
IPC分类号： H04L12/56
摘要： A data transfer system using a high-speed serial interface system that forms a tree structure in which point-to-point communication channels are established for data sending and data receiving independently is provided. The data transfer system includes plural end points each having plural upper ports each of which is connected to a switch of an upper side, wherein each end point includes a port selecting part for selecting a port to be used according to an operation mode of the data transfer system so as to dynamically change the tree structure.
摘要翻译： 提供了一种数据传输系统，其使用形成树形结构的高速串行接口系统，其中为了数据发送和数据接收独立地建立点对点通信信道。 数据传输系统包括多个端点，每个端点具有多个上端口，每个端口连接到上侧的开关，其中每个端点包括端口选择部分，用于根据数据的操作模式选择要使用的端口 传输系统，以动态地改变树结构。
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公开(公告)号：US20070088873A1
公开(公告)日：2007-04-19
申请号：US11511477
申请日：2006-08-29
申请人： Koji Oshikiri , Noriyuki Terao , Junichi Ikeda , Koji Takeo
发明人： Koji Oshikiri , Noriyuki Terao , Junichi Ikeda , Koji Takeo
IPC分类号： G06F3/00
CPC分类号： G06F13/4278 , G06F2213/0026
摘要： An information processing system includes a high-speed serial bus that transmits and receives data independently over communication channels via a tree-structured network including a point-to-point connection, and a control unit that issues a request command based on a request synchronization signal for data with a timing constraint on line synchronous transfer by a line synchronization signal to transmit a plurality of data, including the data with the timing constraint, simultaneously via the high-speed serial bus.
摘要翻译： 一种信息处理系统，包括：高速串行总线，其经由包括点对点连接的树结构化网络在通信信道上独立地发送和接收数据;以及控制单元，其基于请求同步信号发出请求命令 对于具有通过线路同步信号的线路同步传输的定时约束的数据，以经由高速串行总线同时发送包括具有定时约束的数据的多个数据。
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公开(公告)号：US20050254085A1
公开(公告)日：2005-11-17
申请号：US11121060
申请日：2005-05-04
申请人： Koji Oshikiri , Yasuyuki Shindoh , Junichi Ikeda , Koji Takeo , Noriyuki Terao , Atsuhiro Oizumi , Yutaka Maita , Satoru Numakura , Tohru Sasaki
发明人： Koji Oshikiri , Yasuyuki Shindoh , Junichi Ikeda , Koji Takeo , Noriyuki Terao , Atsuhiro Oizumi , Yutaka Maita , Satoru Numakura , Tohru Sasaki
CPC分类号： G06F3/13
摘要： An image forming system comprising a serial communication control part, an image input part, an image output part, an image processing part, a storage part, a printer controller, and a high-speed serial bus. The high-speed serial bus mutually couples the serial communication control part and at least one of the image input part, the image output part, the image processing part, the storage part and the printer controller.
摘要翻译： 一种图像形成系统，包括串行通信控制部分，图像输入部分，图像输出部分，图像处理部分，存储部分，打印机控制器和高速串行总线。 高速串行总线将串行通信控制部分与图像输入部分，图像输出部分，图像处理部分，存储部分和打印机控制器中的至少一个相互耦合。
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公开(公告)号：US20060173986A1
公开(公告)日：2006-08-03
申请号：US11327460
申请日：2006-01-09
申请人： Junichi Ikeda , Koji Oshikiri , Koji Takeo , Noriyuki Terao
发明人： Junichi Ikeda , Koji Oshikiri , Koji Takeo , Noriyuki Terao
IPC分类号： G06F15/173
CPC分类号： H04L49/901 , H04L47/10 , H04L47/30 , H04L49/30 , H04L49/90 , H04L2012/5681
摘要： A communication apparatus is disclosed that includes a transmission circuit configured to transmit transmission data to a communication counterpart; a reception circuit configured to receive reception data from the communication counterpart; a storage device configured as at least two buffers including a transmission buffer that stores the transmission data and a reception buffer that stores the reception data; and an address mapping unit configured to perform address mapping of the buffers including the transmission buffer and the reception buffer on the storage device, and adjust the storage capacity of the transmission buffer and the storage capacity of the reception buffer.
摘要翻译： 公开了一种通信装置，其包括被配置为向通信对方发送传输数据的传输电路; 接收电路，被配置为从所述通信对方接收接收数据; 配置为包括存储发送数据的发送缓冲器和存储接收数据的接收缓冲器的至少两个缓冲器的存储装置; 以及地址映射单元，被配置为在存储装置上执行包括发送缓冲器和接收缓冲器的缓冲器的地址映射，并且调整发送缓冲器的存储容量和接收缓冲器的存储容量。
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公开(公告)号：US20050248584A1
公开(公告)日：2005-11-10
申请号：US11121039
申请日：2005-05-04
申请人： Koji Takeo , Yasuyuki Shindoh , Noriyuki Terao , Koji Oshikiri , Atsuhiro Oizumi , Satoru Numakura , Junichi Ikeda , Tohru Sasaki , Yutaka Maita
发明人： Koji Takeo , Yasuyuki Shindoh , Noriyuki Terao , Koji Oshikiri , Atsuhiro Oizumi , Satoru Numakura , Junichi Ikeda , Tohru Sasaki , Yutaka Maita
CPC分类号： G06F13/4027
摘要： An imaging system that implements a PCI Express high-speed serial interface system is disclosed in which a plurality of point-to-point simplex communication channels are established to realize a data communication network having a tree structure. The imaging system includes a PCI Express high-speed serial interface, and plural independent image processing units as end point devices of the tree structure that are connected by the PCI Express high-speed serial interface.
摘要翻译： 公开了一种实现PCI Express高速串行接口系统的成像系统，其中建立了多个点对点单工通信信道，以实现具有树结构的数据通信网络。 该成像系统包括PCI Express高速串行接口和多个独立的图像处理单元，作为通过PCI Express高速串行接口连接的树结构的端点设备。
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公开(公告)号：US07813362B2
公开(公告)日：2010-10-12
申请号：US11327460
申请日：2006-01-09
申请人： Junichi Ikeda , Koji Oshikiri , Koji Takeo , Noriyuki Terao
发明人： Junichi Ikeda , Koji Oshikiri , Koji Takeo , Noriyuki Terao
IPC分类号： H04L12/00
CPC分类号： H04L49/901 , H04L47/10 , H04L47/30 , H04L49/30 , H04L49/90 , H04L2012/5681
摘要： A communication apparatus is disclosed that includes a transmission circuit configured to transmit transmission data to a communication counterpart; a reception circuit configured to receive reception data from the communication counterpart; a storage device configured as at least two buffers including a transmission buffer that stores the transmission data and a reception buffer that stores the reception data; and an address mapping unit configured to perform address mapping of the buffers including the transmission buffer and the reception buffer on the storage device, and adjust the storage capacity of the transmission buffer and the storage capacity of the reception buffer.
摘要翻译： 公开了一种通信装置，其包括被配置为向通信对方发送传输数据的传输电路; 接收电路，被配置为从所述通信对方接收接收数据; 配置为包括存储发送数据的发送缓冲器和存储接收数据的接收缓冲器的至少两个缓冲器的存储装置; 以及地址映射单元，被配置为在存储装置上执行包括发送缓冲器和接收缓冲器的缓冲器的地址映射，并且调整发送缓冲器的存储容量和接收缓冲器的存储容量。
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公开(公告)号：US07755791B2
公开(公告)日：2010-07-13
申请号：US11399440
申请日：2006-04-07
申请人： Yutaka Maita , Junichi Ikeda , Satoru Numakura , Atsuhiro Oizumi , Koji Oshikiri , Tohru Sasaki , Yasuyuki Shindoh , Koji Takeo , Noriyuki Terao
发明人： Yutaka Maita , Junichi Ikeda , Satoru Numakura , Atsuhiro Oizumi , Koji Oshikiri , Tohru Sasaki , Yasuyuki Shindoh , Koji Takeo , Noriyuki Terao
CPC分类号： H04N1/00236
摘要： An image forming apparatus includes an image input device that reads an image to obtain image data and a printer engine that forms an image on a medium based on image data. A bus of a PCI Express standard is used to transfer data. Storage areas serving as end points of the standard and hardware resources that transmit data and receive image data to and from the storage areas are connected to an identical switch according to the PCI Express standard. Specifically, an input/output area, an image input device, and a printer engine are connected to one switch, and a storage area, a compressor, and a hard disk is connected to another switch.
摘要翻译： 图像形成装置包括：图像输入装置，其读取图像以获得图像数据;以及打印机引擎，其基于图像数据在介质上形成图像。 PCI Express标准的总线用于传输数据。 作为向存储区域发送数据和从存储区域接收图像数据的标准和硬件资源的端点的存储区域根据PCI Express标准连接到相同的交换机。 具体地，输入/输出区域，图像输入装置和打印机引擎连接到一个开关，并且存储区域，压缩器和硬盘连接到另一个开关。
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公开(公告)号：US07454540B2
公开(公告)日：2008-11-18
申请号：US11332203
申请日：2006-01-17
申请人： Koji Oshikiri , Junichi Ikeda , Koji Takeo , Noriyuki Terao
发明人： Koji Oshikiri , Junichi Ikeda , Koji Takeo , Noriyuki Terao
IPC分类号： G06F3/00
CPC分类号： G06F13/4291 , Y02D10/14 , Y02D10/151
摘要： A data transferring system based on the PCI Express standard in which power saving is realized is disclosed. In the data transferring system, a data transferring device transfers image data based on the PCI Express standard by synchronizing with a line synchronizing signal LSYNC. At this time, the data transferring device causes a period between packets (image data) to be transferred in one line cycle of the line synchronizing signal LSYNC to be shorter than a transition period “t1” which is required to transit from a link state L0 to a link state L0s and from the link state L0s to the link state L0. With this, the number of the transition periods “t1” is reduced and the period of the link state L0s is made long.
摘要翻译： 公开了一种基于实现省电的PCI Express标准的数据传输系统。 在数据传送系统中，数据传送装置通过与行同步信号LSYNC同步，基于PCI Express标准传送图像数据。 此时，数据传送装置使得在行同步信号LSYNC的一个行周期中传送的分组（图像数据）之间的周期短于从链接状态过渡所需的过渡期间“t 1” L 0到链路状态L 0 s，并且从链路状态L 0 s到链路状态L 0。 由此，过渡期间“t 1”的数量减少，链路状态L 0 s的周期变长。
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9.发明申请公开(公告)号：US20060187944A1
公开(公告)日：2006-08-24
申请号：US11336863
申请日：2006-01-23
申请人： Koji Takeo , Noriyuki Terao , Junichi Ikeda , Koji Oshikiri
发明人： Koji Takeo , Noriyuki Terao , Junichi Ikeda , Koji Oshikiri
摘要： A data transferring system in which detecting a route from an upper position to a lower position on a tree structure is realized by hardware of communication devices and processes for detecting the above are simplified is disclosed. A root complex broadcasts a search message to a lower node on a tree structure. When a port of the node confirms and receives the search message, the port adds its own information, specifically, the device number of the port, to the data payload part of the search message and sends the search message including the information to a node (end point) located at the lowest position on the tree structure. When the end point receives the search message, the end point sends a reply message to the root complex. The device numbers of the ports where the search message passes through are attached to the reply message.
摘要翻译： 通过通信装置的硬件和用于上述检测的处理来实现检测树结构上的上位置到下位置的路由的数据传送系统被简化。 根复合体将搜索消息广播到树结构上的下层节点。 当节点的端口确认并接收到搜索消息时，端口将其自己的信息，具体地，端口的设备号码添加到搜索消息的数据有效载荷部分，并将包括该信息的搜索消息发送到节点 终点）位于树结构的最低位置。 当终点接收到搜索消息时，终端向根组合发送回复消息。 搜索消息通过的端口的设备号附加到回复消息。
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10.发明授权Information processing system for determining payload size based on packet-to-payload size ratio 失效用于基于分组到有效载荷大小比率来确定有效载荷大小的信息处理系统公开(公告)号：US07536489B2
公开(公告)日：2009-05-19
申请号：US11511477
申请日：2006-08-29
申请人： Koji Oshikiri , Noriyuki Terao , Junichi Ikeda , Koji Takeo
发明人： Koji Oshikiri , Noriyuki Terao , Junichi Ikeda , Koji Takeo
CPC分类号： G06F13/4278 , G06F2213/0026
摘要： An information processing system includes a high-speed serial bus that transmits and receives data independently over communication channels via a tree-structured network including a point-to-point connection, and a control unit that issues a request command based on a request synchronization signal for data with a timing constraint on line synchronous transfer by a line synchronization signal to transmit a plurality of data, including the data with the timing constraint, simultaneously via the high-speed serial bus.
摘要翻译： 一种信息处理系统，包括：高速串行总线，其经由包括点对点连接的树结构化网络在通信信道上独立地发送和接收数据;以及控制单元，其基于请求同步信号发出请求命令 对于具有通过线路同步信号的线路同步传输的定时约束的数据，以经由高速串行总线同时发送包括具有定时约束的数据的多个数据。
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