公开(公告)号：US06119221A

公开(公告)日：2000-09-12

申请号：US959303

申请日：1997-10-28

申请人： Koji Zaiki ,  Tetsuya Tanaka

发明人： Koji Zaiki ,  Tetsuya Tanaka

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/44

CPC分类号： G06F9/3804 ,  G06F9/30094 ,  G06F9/3844

摘要： The present invention intends to provide an instruction prefetching apparatus capable of reducing a delay caused by branch prediction error by prefetching instruction based on a condition of a conditional branch instruction if the condition is already determined at the prefetching of the branch instruction. In the apparatus, a first decoding unit judges whether or not a processed instruction is a conditional branch instruction or not and whether or not the instruction is a condition generate instruction which determines branch condition. A condition determination signal generating means compares an address of a condition generate instruction with the content of a program counter to judge whether the condition is already determined or not, and according to the judgment, outputs a condition determination signal to a condition determination judging unit. In response to the signal input, the condition determination judging unit outputs prefetch address information for generating address to a prefetch address generating unit, using a condition code.

摘要翻译： 本发明旨在提供一种指令预取装置，如果在预取分支指令时已经确定了条件，则能够通过预取指令来减少由分支预测误差引起的延迟。 在该装置中，第一解码单元判断处理的指令是否为条件分支指令，以及该指令是否是确定分支条件的条件生成指令。 条件确定信号发生装置将条件生成指令的地址与程序计数器的内容进行比较，以判断条件是否已经被确定，并且根据该判断，向条件判定判断单元输出条件判定信号。 响应于信号输入，条件确定判断单元使用条件码将预取地址信息输出到预取地址生成单元。

公开(公告)号：US5579494A

公开(公告)日：1996-11-26

申请号：US395373

申请日：1995-02-21

申请人： Koji Zaiki

发明人： Koji Zaiki

IPC分类号： G06F9/45 ,  G06F9/44 ,  G06F15/16

CPC分类号： G06F8/45

摘要： The present invention provides an apparatus for detecting possibility to process in parallel a program including a loop where iteration processing is executed comprising a simulation unit for simulating each iteration of the loop in the program, a variable storage unit for storing information based on the simulation as to a variable whose value is defined in a program statement in relation with information showing a location where in the program the value of the variable is defined, and a judgement unit for judging whether or not parallel processing is possible by referring to the variable storage unit for information of the location;The present invention further provides a program translation apparatus for generating a program applicable to parallel processing based on the detected possibility of executing the program in parallel comprising the simulation unit, the variable storage unit, the judgement unit, and the program generation means for generating the program applicable to parallel processing when it is judged by the judgement unit that parallel processing of the program is possible.

摘要翻译： 本发明提供一种用于检测并行处理包括执行迭代处理的循环的可能性的装置，包括用于模拟程序中循环的每次迭代的模拟单元，用于基于模拟存储信息的可变存储单元 涉及其值在程序语句中与在程序中定义了变量的值的位置相关的信息定义的变量，以及判断单元，用于通过参考可变存储单元来判断是否可以进行并行处理 有关位置的信息; 本发明还提供了一种程序翻译装置，用于基于检测到并行执行程序的可能性来生成适用于并行处理的程序，包括模拟单元，可变存储单元，判断单元和程序生成装置，用于生成 当由判断单元判断可以并行处理程序时，适用于并行处理的程序。

公开(公告)号：US5450554A

公开(公告)日：1995-09-12

申请号：US981002

申请日：1992-11-10

申请人： Koji Zaiki

发明人： Koji Zaiki

IPC分类号： G06F9/45 ,  G06F9/44 ,  G06F15/16 ,  G06F9/455

CPC分类号： G06F8/45

摘要： The present invention provides an apparatus for detecting whether a program having an iterative loop can be processed in parallel. The apparatus includes including a simulation unit for simulating each iteration of the loop in the program, a variable storage unit for storing values of variables that are defined by program statements executed during simulation of the iterations, each stored variable being stored with information showing a location in the program where the value of the variable is defined and the simulated iteration number during which the variable is defined, and a judgement unit for judging that parallel processing is possible when, for each simulated iteration, variables appearing undefined in any program statements of that iteration are defined in preceding program statements within that iteration. The present invention further provides a program translation apparatus for generating a program applicable to parallel processing if a possibility of executing the program in parallel is detected. The program translation apparatus includes the simulation unit, the variable storage unit, the judgement unit, and program generation circuitry for generating the program applicable to parallel processing when it is judged by the judgement unit that parallel processing of the program is possible.

摘要翻译： 本发明提供一种用于检测是否能够并行处理具有迭代循环的程序的装置。 该装置包括模拟单元，用于模拟程序中的循环的每个迭代;变量存储单元，用于存储在迭代模拟期间执行的程序语句定义的变量的值，每个存储的变量存储有显示位置的信息 在定义变量的值的程序中以及定义变量的模拟迭代次数的判断单元，以及用于判断并行处理是可能的判断单元，当对于每个模拟迭代，在该程序语句的任何程序语句中出现未定义的变量时 迭代在该迭代中的前面的程序语句中定义。 本发明还提供一种程序翻译装置，用于在检测到并行执行程序的可能性时，生成适用于并行处理的程序。 程序翻译装置包括模拟单元，可变存储单元，判断单元和程序生成电路，用于当由判断单元判断可以并行处理程序时，产生可应用于并行处理的程序。

公开(公告)号：US5230053A

公开(公告)日：1993-07-20

申请号：US650819

申请日：1991-02-05

申请人： Koji Zaiki

发明人： Koji Zaiki

IPC分类号： G06F9/45 ,  G06F15/16

CPC分类号： G06F8/452

摘要： A compiling method is described whereby a source program written in a conventional high-language for execution by a serial architecture computer can be automatically converted to an object program for parallel execution by a multi-processor computer, without intervention by a programmer. Single loops or nested loops in source program are detected, and where possible are coded for concurrent execution of the outermost loop, with loop interchange in a nested loop, or fission of a loop into a plurality of adjacent loops being performed if necessary to enable concurrentization.

摘要翻译： 描述了一种编译方法，其中用串行架构计算机执行的常规高级语言的源程序可以被自动转换为用于由多处理器计算机并行执行的对象程序，而不需要程序员的干预。 检测到源程序中的单个循环或嵌套循环，并且在可能的情况下对最外层循环的并行执行进行编码，在嵌套循环中进行循环交换，或者如果必要，则执行环到多个相邻循环的分裂以实现并发 。

公开(公告)号：US5634059A

公开(公告)日：1997-05-27

申请号：US322609

申请日：1994-10-13

申请人： Koji Zaiki

发明人： Koji Zaiki

IPC分类号： G06F15/16 ,  G06F9/45 ,  G06F9/30

CPC分类号： G06F8/433 ,  G06F8/452

摘要： The present invention relates to an optimizing compiler apparatus for converting a source program into an object program for use by a parallel computer, which optimizes the number of data transmissions between processing elements for a parallel computer made up of a plurality of processing elements, composed of a loop retrieval unit for retrieving the loop processes from a program, a data transmission calculation unit for calculating the data transmission count generated when each of the loop processes is parallelized, a parallelization determination unit for determining the loop to be parallelized as the loop, out of all the loops in a multiple loop, with the lowest data transmission count and a code generation unit for generating parallelized object code for the determined loop. The data transmission calculation unit is made up of a right side variable retrieval unit for retrieving the variables on the right side of an equation in the loop retrieved by the loop retrieval unit, a variable information storage unit for storing information relating to array variables which should be distributed among every processing element for the part of the program which comes before the loop retrieved by the loop retrieval unit and a calculation unit for calculating the data transmission count based on the variable information for the retrieved right side variable.

摘要翻译： 本发明涉及一种用于将源程序转换为并行计算机使用的目标程序的优化编译装置，其优化由多个处理单元构成的并行计算机的处理单元之间的数据传输次数，该多个处理单元由 循环检索单元，用于从程序中检索循环处理;数据传输计算单元，用于计算当每个循环处理被并行时产生的数据传输计数;平行化确定单元，用于确定要并行的循环作为循环; 具有最低数据传输计数的多循环中的所有循环，以及用于为所确定的循环生成并行化目标代码的代码生成单元。 数据传输计算单元由用于检索循环检索单元检索到的循环中的方程右侧的变量的右侧变量检索单元构成，用于存储与数组变量有关的信息的可变信息存储单元 在循环检索单元检索到的循环之前的程序部分的每个处理单元中分配一个计算单元，该计算单元基于检索到的右侧变量的变量信息来计算数据发送计数。

公开(公告)号：US5056005A

公开(公告)日：1991-10-08

申请号：US337399

申请日：1989-04-13

申请人： Katsuyuki Kaneko ,  Satoshi Gokita ,  Koji Zaiki

发明人： Katsuyuki Kaneko ,  Satoshi Gokita ,  Koji Zaiki

IPC分类号： G06F12/08 ,  G06F5/06 ,  G06F12/00 ,  G06F12/02 ,  G06F13/16 ,  G06F13/36

CPC分类号： G06F5/06

摘要： The buffer device array includes plural buffer devices connected to a bus, wherein the buffer devices hold the respective device addresses and device selection signals in the course of a data transfer operation and subsequently the device addresses and device selection signals held in the devices are used for inspecting devices with respect to whether they can be used for the next data transfer operation, thus enabling the data transfer operation and checking of device status for the next data transfer to be performed in a pipeline fashion and significantly increasing the efficiency of the data transfer operation and of the overall bus utilization.

摘要翻译： 缓冲器阵列包括连接到总线的多个缓冲器件，其中缓冲器件在数据传输操作过程中保持相应的器件地址和器件选择信号，随后器件中保存的器件地址和器件选择信号用于 检查设备是否可以用于下一次数据传输操作，从而能够以流水线方式执行下一次数据传输的数据传输操作和设备状态的检查，并显着提高数据传输操作的效率 和总线利用率。

公开(公告)号：US5764893A

公开(公告)日：1998-06-09

申请号：US509738

申请日：1995-08-01

申请人： Tadashi Okamoto ,  Koji Zaiki ,  Shinji Sasaki ,  Shinji Furuya

发明人： Tadashi Okamoto ,  Koji Zaiki ,  Shinji Sasaki ,  Shinji Furuya

IPC分类号： H04N7/173 ,  H04N21/472 ,  G06F12/02

CPC分类号： H04N21/47202 ,  H04N7/17318 ,  H04N7/17336

摘要： A video-on-demand system divides compressed image data of a video program into image data sections with a predetermined length and stores them in one of a series of storage media in order of reproduction, returning to a first storage medium in the series after reaching a final storage medium in the series, along a story of the video program. The image data sections stored in the storage media are read by time sharing and the original images are reproduced and displayed.

摘要翻译： 视频点播系统将视频节目的压缩图像数据分割为具有预定长度的图像数据部分，并且按照再现顺序将它们存储在一系列存储介质中的一个中，在到达之后返回到系列中的第一存储介质 该系列的最终存储介质，沿着视频节目的故事。 通过时间共享来读取存储在存储介质中的图像数据部分，并且再现和显示原始图像。

公开(公告)号：US06292866B1

公开(公告)日：2001-09-18

申请号：US09280711

申请日：1999-03-30

申请人： Koji Zaiki ,  Takao Yamamoto

发明人： Koji Zaiki ,  Takao Yamamoto

IPC分类号： G06F1324

CPC分类号： G06F13/24

摘要： A processor for controlling execution of instructions stored in a main storage and interruption processing, comprises: interruption processing control device operable to accept an interruption request, analyze an accepted interruption to obtain a cause of the interruption, and generate information indicating a storage position in the main storage of a procedure for processing the cause of the interruption; specific address holding device operable to hold first address information obtained from the information generated by the interruption processing control device; and instruction execution control device operable to decide whether or not the first address information held by the specific address holding device is to be used as information indicating a storage position of an instruction to be executed and control instruction execution according to a decision result.

摘要翻译： 一种用于控制存储在主存储和中断处理中的指令的执行的处理器，包括：中断处理控制装置，可操作以接受中断请求，分析接受的中断以获得中断的原因，并产生指示在该存储位置中的存储位置的信息 主要存储处理中断原因的程序; 特定地址保持装置，用于保存从由中断处理控制装置生成的信息获得的第一地址信息; 以及指令执行控制装置，用于根据判定结果来判定由特定地址保持装置保持的第一地址信息是否被用作指示要执行的指令的存储位置的信息和控制指令执行。

公开(公告)号：US4975872A

公开(公告)日：1990-12-04

申请号：US435049

申请日：1989-11-13

申请人： Koji Zaiki

发明人： Koji Zaiki

IPC分类号： G11C8/16

CPC分类号： G11C8/16

摘要： A memory device comprises an address input, first decoder for decoding an address input applied to the address input means, two-port data storage for storing data, a tag field provided for each of word areas of the data storage means, means for reading data through the first port of the data storage means, data input/output means for writing in and reading out data through the second port of the data storage means, selecting means for selecting data read out through the first port of the data storage means or data externally inputted through the data input/output means, second decoding means for decoding an output data from the selecting means into an address, and control means for controlling reading out of data through the first port of the data storage means, controlling writing in and reading out of data through the second port of the data storage means, and operating in synchronism with an externally supplied clock signal for controlling marking in the tag fields selected sequentially according to address data inputted from the outside through the data input/output means.

摘要翻译： 存储装置包括地址输入，用于解码施加到地址输入装置的地址输入的第一解码器，用于存储数据的两端口数据存储器，为数据存储装置的每个字区域提供的标签字段，用于读取数据的装置 通过数据存储装置的第一端口，用于通过数据存储装置的第二端口写入和读出数据的数据输入/输出装置，用于选择通过数据存储装置的第一端口或数据读出的数据的选择装置 通过数据输入/输出装置外部输入的第二解码装置，用于将来自选择装置的输出数据解码为地址;以及控制装置，用于控制通过数据存储装置的第一端口读出数据，控制写入和读取 通过数据存储装置的第二端口输出数据，并且与外部提供的时钟信号同步地操作，用于控制所选择的序列中的标签字段中的标记 根据从外部通过数据输入/输出装置输入的地址数据。