公开(公告)号：US11288570B2

公开(公告)日：2022-03-29

申请号：US16169676

申请日：2018-10-24

Applicant: Korea Advanced Institute of Science And Technology

Inventor： Yang-Kyu Choi ,  Jae Hur

IPC: G06N3/06 ,  G06N3/08 ,  G11C13/00 ,  G06N3/04 ,  G06N3/063

Abstract: A semiconductor channel based neuromorphic synapse device 1 including a trap-rich layer may be provided that includes: a first to a third semiconductor regions which are formed on a substrate and are sequentially arranged; a word line which is electrically connected to the first semiconductor region; a trap-rich layer which surrounds the second semiconductor region; and a bit line which is electrically connected to the third semiconductor region. When a pulse with positive (+) voltage is applied to the word line, a concentration of electrons emitted from the trap-rich layer to the second semiconductor region increases and a resistance of the second semiconductor region decreases. When a pulse with negative (−) voltage is applied to the word line, a concentration of electrons trapped in the trap-rich layer from the second semiconductor region increases and the resistance of the second semiconductor region increases.

公开(公告)号：US11329157B2

公开(公告)日：2022-05-10

申请号：US16607410

申请日：2019-08-20

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu Choi ,  Jun Woo Son ,  Jae Hur

IPC: H01L21/00 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3205 ,  H01L27/108 ,  H01L29/861

Abstract: A two-terminal biristor in which a polysilicon emitter layer is inserted and a method of manufacturing the same are provided. The method of manufacturing the two-terminal biristor according to an embodiment of the present disclosure includes forming a first semiconductor layer of a first type on a substrate, forming a second semiconductor layer of a second type on the first semiconductor layer, forming a third semiconductor layer of the first type on the second semiconductor layer, and forming a polysilicon layer of the first type on the third semiconductor layer.