公开(公告)号：US12183821B2

公开(公告)日：2024-12-31

申请号：US17346372

申请日：2021-06-14

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu Choi ,  Joon-Kyu Han

IPC: H01L29/78 ,  G06N3/063 ,  H01L29/45

Abstract: Disclosed is a single transistor with a double gate structure for an adjustable firing threshold voltage and a neuromorphic system using the same. A single transistor neuron with a double gate structure according to an example embodiment includes a barrier material layer formed on a semiconductor substrate and comprising a hole barrier material or an electron barrier material; a floating body layer formed on the barrier material layer; a source and a drain formed at both sides of the floating body layer, respectively; a driving gate formed at a first side of the floating body layer without contacting the source and the drain; a control gate formed at a second side of the floating body layer without contacting the source and the drain; and a gate insulating film formed between the floating body layer and the driving gate and between the floating body layer and the control gate.

公开(公告)号：US20220223705A1

公开(公告)日：2022-07-14

申请号：US17437368

申请日：2021-07-29

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu Choi ,  Myung-Su Kim

IPC: H01L29/423 ,  G11C16/10 ,  H01L29/788 ,  H01L21/28 ,  H01L29/66

Abstract: A steep-slope field-effect transistor and a fabrication method thereof are disclosed. The steep-slope field-effect transistor according to an embodiment of the inventive concept includes a source, a channel region, and a drain formed on a substrate; a gate insulating film formed on an upper portion of the channel region; a floating gate formed on an upper portion of the gate insulating film; a transition layer formed on an upper portion of the floating gate; and a control gate formed on an upper portion of the transition layer. The steep-slope field-effect transistor applies a reference potential or more to the control gate to discharge or bring in at least one charge stored in the floating gate.

公开(公告)号：US11031467B2

公开(公告)日：2021-06-08

申请号：US15930804

申请日：2020-05-13

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu Choi ,  Byung-Hyun Lee ,  Min-Ho Kang

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L21/3065 ,  H01L21/265 ,  H01L21/324 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/308 ,  H01L29/417

Abstract: Disclosed is a field effect transistor based on vertically integrated gate-all-around multiple nanowire channels including forming vertically integrated multiple nanowire channels in which a plurality of nanowires is vertically integrated, forming an interlayer dielectric layer (ILD) on the vertically integrated multiple nanowire channels, forming a hole in the interlayer dielectric layer such that at least some of the vertically integrated multiple nanowire channels are exposed, and forming a gate dielectric layer on the interlayer dielectric layer to fill the hole, wherein the forming of the gate dielectric layer on the interlayer dielectric layer to fill the hole includes depositing the gate dielectric layer on the interlayer dielectric layer to surround at least some of the vertically integrated multiple nanowire channels that are exposed though the hole. Nanowires may include various shapes of current channels that have efficient structures for current path. The cross section of the nanowire can be one of a circle shape, squared shape, rectangular shape, round shape, triangular shape, rhombus shape, eclipse shape, and others.

公开(公告)号：US09997596B2

公开(公告)日：2018-06-12

申请号：US15041559

申请日：2016-02-11

Applicant: Korea Advanced Institute of Science And Technology

Inventor： Yang-Kyu Choi ,  Jun-Young Park

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/266 ,  H01L21/308 ,  H01L29/66 ,  H01L21/306 ,  H01L29/423

CPC classification number: H01L29/0673 ,  H01L21/02694 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/3081 ,  H01L29/42392 ,  H01L29/66356 ,  H01L29/66568 ,  H01L29/7391

Abstract: A tunneling field-effect transistor may be provided that includes: a substrate; a source which is formed on the substrate and into which p+ type impurity ion is injected; a drain which is formed on the substrate and into which n+ type impurity ion is injected; a plurality of vertically stacked nanowire channels which are formed on the substrate; a gate insulation layer which is formed on the plurality of nanowire channels; and a gate which is formed on the gate insulation layer. As a result, it is possible to generate a higher driving current without changing the length of the gate and the area of the channel (degree of integration).

公开(公告)号：US11922988B2

公开(公告)日：2024-03-05

申请号：US17674301

申请日：2022-02-17

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu Choi ,  Myung-Su Kim

IPC: G11C11/24 ,  G11C11/404 ,  G11C11/4096

CPC classification number: G11C11/404 ,  G11C11/4096

Abstract: Disclosed are a DRAM device capable of storing charges for a long time and an operating method thereof. According to an embodiment, a DRAM device includes a channel region formed on a substrate, a gate insulating film region formed on the channel region, a floating gate region formed on the gate insulating film region, a transition layer region formed on the floating gate region, and a control gate region formed on the transition layer region and generating a potential difference with the floating gate region in response to a fact that a potential that is not less than a reference potential is applied and releasing at least one charge stored in the floating gate region or storing the at least one charge into the floating gate region, by generating a transition current due to the potential difference.

公开(公告)号：US20170236901A1

公开(公告)日：2017-08-17

申请号：US15428727

申请日：2017-02-09

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu Choi ,  Byung-Hyun Lee ,  Min-Ho Kang

IPC: H01L29/06 ,  H01L21/3065 ,  H01L21/265 ,  H01L21/324 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L21/027

CPC classification number: H01L29/0673 ,  H01L21/0274 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696

Abstract: Disclosed is a method of manufacturing a junctionless transistor based on vertically integrated gate-all-around multiple nanowire channels including forming vertically integrated multiple nanowire channels in which a plurality of nanowires is vertically integrated, forming an interlayer dielectric layer (ILD) on the vertically integrated multiple nanowire channels, forming a hole in the interlayer dielectric layer such that at least some of the vertically integrated multiple nanowire channels is exposed, and forming a gate dielectric layer on the interlayer dielectric layer to fill the hole, wherein the forming of the gate dielectric layer on the interlayer dielectric layer to fill the hole includes depositing the gate dielectric layer on the interlayer dielectric layer to surround at least some of the vertically integrated multiple nanowire channels which is exposed though the hole.

公开(公告)号：US11288570B2

公开(公告)日：2022-03-29

申请号：US16169676

申请日：2018-10-24

Applicant: Korea Advanced Institute of Science And Technology

Inventor： Yang-Kyu Choi ,  Jae Hur

IPC: G06N3/06 ,  G06N3/08 ,  G11C13/00 ,  G06N3/04 ,  G06N3/063

Abstract: A semiconductor channel based neuromorphic synapse device 1 including a trap-rich layer may be provided that includes: a first to a third semiconductor regions which are formed on a substrate and are sequentially arranged; a word line which is electrically connected to the first semiconductor region; a trap-rich layer which surrounds the second semiconductor region; and a bit line which is electrically connected to the third semiconductor region. When a pulse with positive (+) voltage is applied to the word line, a concentration of electrons emitted from the trap-rich layer to the second semiconductor region increases and a resistance of the second semiconductor region decreases. When a pulse with negative (−) voltage is applied to the word line, a concentration of electrons trapped in the trap-rich layer from the second semiconductor region increases and the resistance of the second semiconductor region increases.

公开(公告)号：US10956622B2

公开(公告)日：2021-03-23

申请号：US16032630

申请日：2018-07-11

Applicant: Korea Advanced Institute of Science And Technology

Inventor： Yang-Kyu Choi ,  Jun-Young Park

IPC: G06F21/79 ,  G11C13/00 ,  G11C16/34 ,  H05B3/00 ,  G11C16/22 ,  G11C16/30 ,  G11C11/16 ,  G11C16/14 ,  G11C7/04 ,  G11C16/10 ,  H05B3/26 ,  H01L23/34

Abstract: The present invention provides a thermal hardware-based data security device that is capable of physically, hardware-wise, and permanently erasing data stored in a memory and of enabling a storage device to be reused, and a method thereof. The thermal hardware-based data security device includes: a memory chip capable of storing data; a heater module which supplies heat to permanently erase the data stored in a memory cell within the memory chip; and a switch module which short-circuits the heater module between a power supply unit and a ground when switched on, and thus, controls the heater module to be operated.

公开(公告)号：US09728539B2

公开(公告)日：2017-08-08

申请号：US15044702

申请日：2016-02-16

Applicant: Korea Advanced Institute of Science And Technology

Inventor： Yang-Kyu Choi ,  Jun-Young Park ,  Byung-Hyun Lee ,  Dae-Chul Ahn

IPC: G11C11/24 ,  H01L27/108 ,  H01L29/06 ,  H01L29/165 ,  H01L29/16 ,  H01L29/161 ,  H01L21/265 ,  H01L21/308 ,  H01L21/02 ,  H01L29/423 ,  G11C11/409 ,  G11C7/10

CPC classification number: H01L27/10802 ,  G11C7/1072 ,  G11C11/404 ,  G11C11/409 ,  G11C11/565 ,  G11C2211/4016 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/3081 ,  H01L21/3083 ,  H01L29/0673 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439

Abstract: A multi-bit capacitorless DRAM according to the embodiment of the present invention may be provided that includes: a substrate; a source and a drain formed on the substrate; a plurality of nanowire channels formed on the substrate; a gate insulation layer formed in the plurality of nanowire channels; and a gate formed on the gate insulation layer. Two or more nanowire channels among the plurality of nanowire channels have different threshold voltages. Each of the nanowire channels includes: a silicon layer; a first epitaxial layer which is formed to surround the silicon layer; and a second epitaxial layer which is formed to surround the first epitaxial layer. As a result, the high integration multi-bit capacitorless DRAM which operates at multi-bits can be implemented and a performance of accumulating excess holes can be improved by using energy band gap.

公开(公告)号：US11869950B2

公开(公告)日：2024-01-09

申请号：US17437368

申请日：2021-07-29

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu Choi ,  Myung-Su Kim

IPC: G11C11/34 ,  H01L29/423 ,  H01L21/28 ,  G11C16/10 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L29/42324 ,  G11C16/10 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7881

Abstract: A steep-slope field-effect transistor and a fabrication method thereof are disclosed. The steep-slope field-effect transistor according to an embodiment of the inventive concept includes a source, a channel region, and a drain formed on a substrate; a gate insulating film formed on an upper portion of the channel region; a floating gate formed on an upper portion of the gate insulating film; a transition layer formed on an upper portion of the floating gate; and a control gate formed on an upper portion of the transition layer. The steep-slope field-effect transistor applies a reference potential or more to the control gate to discharge or bring in at least one charge stored in the floating gate.