公开(公告)号：US20130132793A1

公开(公告)日：2013-05-23

申请号：US13678812

申请日：2012-11-16

Applicant: Korea Advanced Institute of Science and Technolo

Inventor： Jeong Seok HA ,  Sung Gun CHO

IPC: H03M13/15

CPC classification number: H03M13/2912 ,  H03M13/152 ,  H03M13/2918 ,  H03M13/2927 ,  H03M13/3707

Abstract: The present disclosure relates to a BCH encoding, decoding, and multi-stage decoding circuits and method, and an error correction circuit of a flash memory device using the same. The concatenated BCH multi-stage decoding circuit includes: a first stage encoding unit that receives a part or all of data input to a flash memory device, performs BCH encoding, and outputs a first output BCH code or a parity bit thereof; an interleaving unit that receives a part or all of data input to the flash memory device, interleaves, and outputs the data, and a second stage encoding unit that performs BCH encoding of the BCH code or data that is the output of the interleaving unit, and outputs a second output BCH code or a parity bit thereof.

Abstract translation: 本公开涉及使用该BCH编码，解码和多级解码电路和方法的闪存器件的纠错电路。 串联BCH多级解码电路包括：第一级编码单元，其接收输入到闪速存储器件的数据的一部分或全部，执行BCH编码，并输出第一输出BCH码或其奇偶校验位; 接收输入到闪速存储器件的数据的一部分或全部，交织并输出数据的交错单元，以及执行作为交织单元的输出的BCH码或数据的BCH编码的第二级编码单元， 并输出第二输出BCH码或其奇偶校验位。