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    FLASH MEMORY SYSTEM AND OPERATING METHOD THEREOF
    3.
    发明申请
    FLASH MEMORY SYSTEM AND OPERATING METHOD THEREOF 有权
    闪存存储器系统及其操作方法

    公开(公告)号：US20160210190A1

    公开(公告)日：2016-07-21

    申请号：US14802833

    申请日：2015-07-17

    申请人： SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

    发明人： Jeong-Seok HA ,  Dae-Sung KIM ,  Su-Hwang JEONG

    IPC分类号： G06F11/10 ,  H03M13/29 ,  H03M13/15 ,  G11C29/52

    CPC分类号： G06F11/1068 ,  G06F11/1012 ,  G11C11/5642 ,  G11C16/3418 ,  G11C29/42 ,  G11C29/52 ,  H03M13/152 ,  H03M13/2906 ,  H03M13/2912 ,  H03M13/2927 ,  H03M13/2963 ,  H03M13/453

    摘要： An operation method of a flash memory system includes: performing hard decision decoding on a codeword, which is encoded in units of message blocks with row constituent codes and column constituent codes according to a block-wise concatenated BCH (BC-BCH) method; identifying a location of an error message block to which the hard decision decoding fails among a plurality of the message blocks, when the hard decision decoding fails; generating soft decision information corresponding to the row constituent codes and the column constituent codes of the error message block; and performing soft decision decoding on the error message block based on the soft decision information.

    摘要翻译： 闪速存储器系统的操作方法包括：根据块式级联的BCH（BC-BCH）方法，对具有行组成码和列组成码的消息块单元编码的码字执行硬判决解码; 当硬判决解码失败时，识别多个消息块中的硬判决解码失败的错误消息块的位置; 产生对应于错误消息块的行组成码和列组成码的软判决信息; 以及基于所述软判决信息对所述错误消息块执行软判决解码。

    Encoding, decoding, and multi-stage decoding circuits for concatenated BCH, and error correction circuit of flash memory device using the same
    4.
    发明授权
    Encoding, decoding, and multi-stage decoding circuits for concatenated BCH, and error correction circuit of flash memory device using the same 有权
    用于级联BCH的编码，解码和多级解码电路，以及使用其的闪速存储器件的纠错电路

    公开(公告)号：US09166626B2

    公开(公告)日：2015-10-20

    申请号：US13678812

    申请日：2012-11-16

    申请人： Korea Advanced Institute of Science and Technology

    发明人： Jeong Seok Ha ,  Sung Gun Cho

    IPC分类号： H03M13/29 ,  H03M13/37 ,  H03M13/15

    CPC分类号： H03M13/2912 ,  H03M13/152 ,  H03M13/2918 ,  H03M13/2927 ,  H03M13/3707

    摘要： The present disclosure relates to a BCH encoding, decoding, and multi-stage decoding circuits and method, and an error correction circuit of a flash memory device using the same. The concatenated BCH multi-stage decoding circuit includes: a first stage encoding unit that receives a part or all of data input to a flash memory device, performs BCH encoding, and outputs a first output BCH code or a parity bit thereof; an interleaving unit that receives a part or all of data input to the flash memory device, interleaves, and outputs the data, and a second stage encoding unit that performs BCH encoding of the BCH code or data that is the output of the interleaving unit, and outputs a second output BCH code or a parity bit thereof.

    摘要翻译： 本公开涉及使用该BCH编码，解码和多级解码电路和方法的闪存器件的纠错电路。 串联BCH多级解码电路包括：第一级编码单元，其接收输入到闪速存储器件的数据的一部分或全部，执行BCH编码，并输出第一输出BCH码或其奇偶校验位; 接收输入到闪速存储器件的数据的一部分或全部，交织并输出数据的交错单元，以及执行作为交织单元的输出的BCH码或数据的BCH编码的第二级编码单元， 并输出第二输出BCH码或其奇偶校验位。

    CONCATENATED ERROR CORRECTION DEVICE
    5.
    发明申请
    CONCATENATED ERROR CORRECTION DEVICE 有权
    已定义的错误修正设备

    公开(公告)号：US20150155888A1

    公开(公告)日：2015-06-04

    申请号：US14555656

    申请日：2014-11-27

    申请人： KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

    发明人： Jaekyun MOON ,  Geunyeong YU

    IPC分类号： H03M13/29 ,  G06F11/10

    CPC分类号： H03M13/2912 ,  G06F11/1012 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/293 ,  H03M13/3761

    摘要： A concatenated error correction device may be provided that includes: a first encoder which encodes a plurality of blocks arranged in a column direction and a row direction into a block-wise product code consisting of column codes and row codes by applying a first error correction code to the blocks in each of the column direction and the row direction; and a second encoder which receives K number of source symbols and applies a second error correction code to the source symbols, and then encodes into N number of symbols including N-K number of parity symbols. The N number of symbols form the plurality of blocks. K and N are natural numbers.

    摘要翻译： 可以提供一种级联纠错装置，其包括：第一编码器，通过应用第一纠错码将由列方向和行方向排列的多个块编码成由列码和行码组成的块式产品代码 到列方向和行方向中的每一个的块; 以及第二编码器，其接收K个源符号，并向源符号应用第二纠错码，然后将其编码为包括N-K个奇偶校验符号的N个符号。 N个符号形成多个块。 K和N是自然数。