公开(公告)号：US12268008B2

公开(公告)日：2025-04-01

申请号：US17743314

申请日：2022-05-12

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Sanghun Jeon ,  Youngin Goh

IPC: H10B53/20

Abstract: Disclosed are a 3D non-volatile memory, an operating method thereof, and a manufacturing method thereof. The 3D non-volatile memory includes a bit line formed to extend in a vertical direction and horizontal structures contacting the bit line while being formed to extend in a horizontal direction and being space in the vertical direction. Each of the horizontal structures includes a ferroelectric layer contacting the bit line, a middle metal layer surrounded by the ferroelectric layer, a dielectric layer surrounded by the middle metal layer, and a word line surrounded by the dielectric layer.

公开(公告)号：US11729992B2

公开(公告)日：2023-08-15

申请号：US17321814

申请日：2021-05-17

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Sanghun Jeon ,  Youngin Goh

IPC: H01L21/00 ,  H10B53/30 ,  H01L49/02

CPC classification number: H10B53/30 ,  H01L28/60

Abstract: Provided is a nonvolatile memory device including a lower electrode on a substrate, an upper electrode on the lower electrode, a tunnel barrier pattern between the lower electrode and the upper electrode, and a fixed charge pattern in contact with the lower electrode and spaced apart from the tunnel barrier pattern with the lower electrode therebetween. The tunnel barrier pattern includes an anti-ferroelectric material. The lower electrode includes a first material. The upper electrode includes a second material. The first material and the second material have different work functions.

公开(公告)号：US11950429B2

公开(公告)日：2024-04-02

申请号：US17078672

申请日：2020-10-23

Applicant: Samsung Electronics Co., Ltd. ,  KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Sanghun Jeon

IPC: H10B53/00 ,  G11C11/22 ,  H01L29/51 ,  H01L29/78 ,  H10B53/20

CPC classification number: H10B53/00 ,  G11C11/221 ,  H01L29/516 ,  H01L29/78391 ,  H10B53/20

Abstract: The present invention relates to ferroelectric capacitors, transistors, memory device, and method of manufacturing ferroelectric devices. The ferroelectric capacitor includes a first electrode, a second electrode facing the first electrode, a ferroelectric layer between the first electrode and the second electrode, and an interfacial layer between the ferroelectric layer and the first electrode or between the ferroelectric layer and the second electrode. The ferroelectric layer includes hafnium-based oxide. The interfacial layer includes HfO2.

公开(公告)号：US12279436B2

公开(公告)日：2025-04-15

申请号：US18197189

申请日：2023-05-15

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Sanghun Jeon ,  Taeho Kim

IPC: H10B51/30 ,  G11C11/22 ,  H10B51/20

Abstract: Disclosed are a non-volatile memory including a negative capacitance blocking oxide layer, an operating method of the same, and a manufacturing method of the same. The non-volatile memory may include a tunneling oxide layer formed on a channel; a charge storage layer formed on one surface of the tunneling oxide layer; a negative capacitance blocking oxide layer in which a dielectric layer and an imprinted polarization layer are sequentially configured on one surface of the charge storage layer; and a gate formed on one surface of the negative capacitance blocking oxide layer.